Design Techniques for emc – Part 1 Circuit Design, and Choice of Components




НазваниеDesign Techniques for emc – Part 1 Circuit Design, and Choice of Components
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Design Techniques for EMCPart 1 Circuit Design, and Choice of Components

By Eur Ing Keith Armstrong CEng MIEE MIEEE

Partner, Cherry Clough Consultants, Associate of EMC-UK

http://64.70.157.146/archive/old_archive/990208.htm


This is the first in a series of six articles on best-practice EMC techniques in electrical/electronic/mechanical hardware design, to be published in this journal over the following year. The series is intended for the designer of electronic products, from building block units such as power supplies, single-board computers, and “industrial components” such as motor drives, through to stand-alone or networked products such computers, audio/video/TV, instruments, etc.


These articles were first published in the EMC Journal as a series during 1999. This version includes a number of corrections, modifications, and additions, many of which have been made as a result of correspondence with the following, to whom I am very grateful: Feng Chen, Kevin Ellis, Neil Helsby, Mike Langrish, Tom Liszka, Alan Keenan, T Sato, and John Woodgate. I am also indebted to Tom Sato for translating these articles into Japanese and posting them on his website: http://member.nifty.ne.jp/tsato/, as well as suggesting a number of improvements.


The techniques covered in these six articles are:

1) Circuit design (digital, analogue, switch-mode, communications), and choosing components

2) Cables and connectors

3) Filters and transient suppressors

4) Shielding

5) PCB layout (including transmission lines)

6) ESD, electromechanical devices, and power factor correction


A textbook could be written about any one of the above topics (and many have), so this magazine article format can do no more than introduce the various issues and point to the most important of the best-practice techniques.


Before starting on the above list of topics it is useful see them in the context of the ideal EMC lifecycle of a new product design and development project.


The project EMC lifecycle

The EMC issues in a new project lifecycle are summarized below:

  • Establishment of the target electromagnetic specifications for the new product, including:

    • The electromagnetic environment it must withstand (including continuous, high-probability, and low-probability disturbance events) and the degradation in performance to be allowed during disturbance events;

    • Its possible proximity to sensitive apparatus and allowable consequences, hence the emissions specifications;

    • Whether there are any safety issues requiring additional electromagnetic performance specifications. Safety compliance is covered by safety directives, not by EMC Directive;

    • All the EMC standards to be met, regulatory compliance documentation to be created, and how much “due diligence” to apply in each case (consider all markets, any customers’ in-house specifications, etc.).




      • System design:

        • Employ system-level best-practices (“bottom-up”);

        • Flow the “top-level” EMC specifications down into the various system blocks (“top-down”).




          • System block (electronic) designs:

            • Employ electrical/electronic hardware design best-practices (“bottom-up”) (covered by these six articles);

            • Simulate EMC of designs prior to creating hardware, perform simple EMC tests on early prototypes, more standardized EMC tests on first production issue.




              • Employ best-practice EMC techniques in software design.




  • Achieve regulatory compliance for all target markets.




  • Employ EMC techniques in QA to control:

    • All changes in assembly, including wiring routes and component substitutions;

    • All electrical/electronic/mechanical design modifications and software bug-fixes;

    • All variants.




      • ·Sell only into the markets originally designed for;

        • To add new markets go through the initial electromagnetic specification stage again.




          • Investigate all complaints of interference problems




            • Feed any resulting improvements to design back into existing designs and new products (a corrective action loop).


This may look quite daunting, but it is only what successful professional marketers and engineers already know to do, so as not to expose their company to excessive commercial and/or legal risks.


As electronic technology becomes more advanced, more advanced management and design techniques (such as EMC) are required. There is no escaping the ratcheting effects of new electronic technologies if a company wants to remain profitable and competitive. But new electronics technologies are creating the worlds largest market, expected to exceed US$1 trillion annually in value (that’s $1 million million) within a couple of years and continue to increase at 15% or so per annum after that. Rewards are there for those that can take the pace.


The following outlines a number of the most important best-EMC-practices. They deal with “what” and “how” issues, rather than with why they are needed or why they work. A good understanding of the basics of EMC is a great benefit in helping to prevent under or over-engineering, but goes beyond the scope of these articles.


Table of contents for Part 1

1. Circuit design and choice of components for EMC

1.1 Digital components and circuit design for EMC

1.1.1 Choosing components

1.1.2 Batch and mask-shrink problems

1.1.3 IC sockets are bad

1.1.4 Circuit techniques

1.1.5 Spread-spectrum clocking

1.2 Analogue components and circuit design

1.2.1 Choosing analogue components

1.2.2 Preventing demodulation problems

1.2.3 Other analogue circuit techniques

1.3 Switch-mode design

1.3.1 Choice of topology and devices

1.3.2 Snubbing

1.3.3 Heat-sinks

1.3.4 Rectifiers

1.3.5 Problems and solutions relating to magnetic components

1.3.6 Spread-spectrum clocking for switch-mode

1.4 Signal communication components and circuit design

1.4.1 Non-metallic communications are best

1.4.2 Techniques for metallic communications

1.4.3 Opto-isolation

1.4.4 External I/O protection

1.4.5 “Earth – free” and “floating” communications

1.4.6 Hazardous area and intrinsically safe communications

1.4.7 Communication protocols

1.5 Choosing passive components

1.6 References:

1. Circuit design and choice of components for EMC

Correct choice of active and passive components, and good circuit design techniques used from the beginning of a new design and development project, will help achieve EMC compliance in the most cost-effective way, reducing the cost, size, and weight of the eventual filtering and shielding required.


These techniques also improve digital signal integrity and analogue signal-to-noise, and can save at least one iteration of hardware and software. This will help new products achieve their functional specifications, and get to market, earlier. These EMC techniques should be seen as a part of a company’s competitive edge, for maximum commercial benefit.


1.1 Digital components and circuit design for EMC

1.1.1 Choosing components

Most digital IC manufacturers have at least one glue-logic range with low emissions, and a few versions of I/O chips with improved immunity to ESD. Some offer VLSI in “EMC friendly” versions (some “EMC” microprocessors have 40 dB lower emissions than regular versions).


Most digital circuits are clocked with square-waves, which have a very high harmonic content, as shown by Figure 1.




The faster the clock rate and the sharper the edges, the higher the frequency and emissions levels of the harmonics.


So always choose the slowest clock rate, and the slowest edge rate that will still allow the product to achieve its specification. Never use AC when HC will do. Never use HC when CMOS 4000 will do.


Choose integrated circuits with advanced signal integrity and EMC features, such as:

  • Adjacent, multiple, or centre-pinned power and ground.

Adjacent ground and power pins, multiple ground and power pins, and centre-pinned power and ground all help maximize the mutual inductance between power and ground current paths, and minimize their self-inductance, reducing the current loop area of the power supply currents and helping decoupling to work more effectively. This reduces problems for EMC and ground-bounce.


  • Reduced output voltage swing and controlled slew rates.

Reduced output voltage swing and controlled slew rates both reduce the dV/dt and dI/dt of the signals and can reduce emissions by several dB. Although these techniques improve emissions, they could worsen immunity in some situations, so a compromise may be needed


  • Transmission-line matching I/Os.

ICs with outputs capable of matching to transmission-lines are needed when high-speed signals have to be sent down long conductors. E.g. bus drivers are available which will drive a 25W shunt-terminated load. These will drive 1 off 25W transmission line (e.g. RAMBUS); or will drive 2 off 50W lines, 4 off 100W lines, or 6 off 150W lines (when star-connected).


  • Balanced signaling.

Balanced signaling uses ± (differential) signals and does not use 0V as its signal return. Such ICs are very helpful when driving high-speed signals (e.g. clocks > 66MHz) because they help to preserve signal integrity and also can considerably improve common-mode emissions and immunity.


  • Low ground bounce.

ICs with low ground-bounce will generally be better for EMC too.


  • Low levels of emissions.

Most digital IC manufacturers offer glue-logic ranges with low emissions. For instance ACQ and ACTQ have lower emissions than AC and ACT. Some offer VLSI in “EMC friendly” versions. For example Philips has at least two 80C51 microprocessor models which are up to 40dB quieter than their other 80C51 products.


  • Non-saturating logic preferred.

Non-saturating logic is preferred, because its rise and fall times tend to be smoother (slew-rate controlled) and so contain lower levels of high-order harmonics than saturating logic such as TTL.


  • High levels of immunity to ESD and other disturbing phenomena.

Serial communications devices (e.g. RS232, RS 485) are available with high levels of immunity to ESD and other transients on their pins. If their immunity performance isn’t specified to at least the same standards and levels that you need for your product, additional suppression components will be needed.


  • Low input capacitance.

Low input capacitance devices help to reduce the current peaks which occur whenever a logic state changes, and hence reduce the magnetic field emissions and ground return currents (both prime causes of digital emissions).


  • Low levels of power supply transient currents.

Totem-pole output stages in digital ICs go through a brief period when both devices are on, whenever they switch from one state to the other. During this brief period the supply rail is shorted to 0V, and the power supply current transient can exceed the signal’s output current. Both the transient current (sometimes called the ‘shoot-through’ current) and the voltage noise it causes on the power rails are prime causes of emissions. Relevant parameters may include the transient current’s peak value, its dI/dt (or frequency spectrum) and its total charge, any/all of which can be important for the correct design of the power supply’s decoupling. ICs with specified low levels of power supply transients should be chosen where possible.


  • Output-drive capability no larger than need for the application.

The output drive current of an IC (especially a bus driver) should be no larger than is needed. Drivers rated for a higher current have larger output transistors, which can mean considerably larger power supply transients. Their increased drive capability can also mean that the traces they drive can experience faster rise and fall-times than are needed, leading to increased overshoot and ringing problems for signal integrity as well as higher levels of RF emissions.


All of the above should have guaranteed minimum or maximum (as appropriate) specifications (or at least typical specifications) in their data sheets.


Second-sourced parts (with the same type number and specifications but from different manufacturers) can have significantly different EMC performance – something it is important to control in production to ensure continuing compliance in serial manufacture. If products haven’t been EMC tested with the alternative ICs fitted, it will be best to stick with a single source.


Suppliers of high-technology ICs may provide detailed EMC design instructions, as Intel does for its Pentium MMO chips. Get them, and follow them closely. Detailed EMC design advice shows that the manufacturer cares about the real needs of his customers, and may tip the balance when choosing devices.


Some FPGAs (and maybe other ICs) now have the ability to program the slew rate, output drive capability and/or output impedance of their drive signals. Their drive characteristics can be adjusted to give better signal integrity and/or EMC performance and this should help save time in development by reducing the need to replace ICs, change the values of components on the PCB, or modify the PCB layout.


Where ICs’ EMC performances are unknown, correct selection at an early design stage can be made by EMC testing a variety of contenders in a simple standard functional circuit that at least runs their clocks, preferably performs operations on high-rate data too.


Testing for emissions can easily be done in a few minutes on a standard test bench with a close-field magnetic loop probe connected to a spectrum analyzer (or a wideband oscilloscope). Some devices will be obviously much quieter than others. Testing for immunity can use the same probe connected to the output of a signal generator (continuous RF or transient) – but if it is a proprietary probe (and not just a shorted turn of wire) first check that its power handling is adequate.


Close-field probes need to be held almost touching the devices or PCBs being probed. To locate the “hottest spots” and maximize probe orientation they should first be scanned in a horizontal and vertical matrix over the whole area (holding the probe in different orientations at 90o to each other for each direction), then concentrating on the areas with the strongest signals.


1.1.2 Batch and mask-shrink problems

Some batches of ICs with the same type numbers and manufacturers can have different EMC performance.


Semiconductor manufacturers are always trying to improve the yields they get from a silicon wafer, and one way of doing this is to mask-shrink the ICs so they are smaller. Mask-shrunk ICs can have significantly different EMC performance, because smaller device means:

  • less energy is required (in terms of voltage, current, power or charge) to control the internal transistors, which can mean lowered levels of immunity




  • thinner oxide layers, which can mean less immunity to damage from ESD, surge, or over-voltage




  • lower thermal capacity of internal transistors can mean higher susceptibility to electrical overstress




  • faster operation of transistors, which can mean higher levels of emissions and higher frequencies of emissions.


Large users can usually arrange to get advance warnings of mask-shrinks so they can buy enough of the ‘old’ ICs to keep them in production while they find out how to deal with the changed EMC from the new mask-shrunk IC.


It is possible to perform simple goods-in checks of IC EMC performance to see whether a new batch has different EMC performance, for whatever reason. This helps discover problems early on, and so save money.


Alternatively, sample-based EMC testing in serial manufacture is required to avoid shipping non-compliant or unreliable products, but it is much more costly to detect components with changed EMC performance this way than it is at goods-in.


1.1.3 IC sockets are bad

IC sockets are very bad for EMC, and directly soldered surface-mount chips (or chip and wire, or similar direct chip termination techniques) are preferred. Smaller ICs with smaller bond wires and lead frames are better, with BGA and similar styles of chip packaging being the best possible to date.


Often the emissions and susceptibility of non-volatile memory mounted on sockets (or, worse still, sockets containing battery backup) ruin the EMC of an otherwise good design. Field-programmable low-profile SMD non-volatile memory ICs soldered direct to the PCB are preferred.


Motherboards with ZIF sockets and spring-mounted heat-sinks for their processors (to allow easy upgrading) are going to require additional costs on filtering and shielding, even so it will help to choose surface-mounted ZIF sockets with the shortest lengths of internal metalwork for their contacts.


1.1.4 Circuit techniques

  • Level detection (rather than edge-detection) preferred for control inputs and key-presses.

Use level detection ICs for all control inputs and key-presses. Edge detecting ICs are very sensitive to high-frequency interference such as ESD. (If control signals need to use such very high rates that they need to use edge-detecting devices, they should be treated for EMC as for any other high-speed communication link.)


  • Use digital edge-rates that are as slow and smooth as possible should be used wherever possible, especially for long PCB traces and wired interconnections (without compromising skew limits).

Where skew is not a problem very slow edges should be used (could be ‘squared-up’ with Schmitt gates where locally necessary).


  • On prototype PCBs allow for control of logic edge speed or bandwidths (e.g. with soft ferrite beads, series resistors, RC or Tee filters at driven ends).

Many IC data books don’t specify their output rise or fall times at all (or only specify the maximum times, leaving typical rates unspecified). Because it is often necessary to control unwanted harmonics, it is advisable to make provision for control of logic edge speed or bandwidths, (on prototype PCBs at least).

Series resistors or ferrite beads are usually the best way to control edge rates and unwanted harmonics, although R-C-R tee filters can also be used and may be able to give better control of harmonics where transmission lines are used. (simple capacitor to ground can increase output transient currents and increase emissions.)


  • Keep load capacitance low.

This reduces the output current transient when the logic state changes over and helps to reduce magnetic field emissions, ground bounce, and transient voltage drops in the ground plane and power supply, all important issues for EMC.


  • Fit pull-ups for open-collector drivers near to their output devices, using the highest resistor values that will work.

This helps reduce the current loop area and the maximum current, and so helps to reduce magnetic field emissions. However, this could worsen immunity performance in some situations, so a compromise may be needed.


  • Keep high speed devices far away from connectors and wires.

Coupling (e.g. crosstalk) can occur between the metallisation, bond wires, and lead frame inside an IC and other conductors nearby. These coupled voltages and currents can greatly increase CM emissions at high frequencies. So keep high speed devices away from all connectors, wires, cables, and other conductors. The only exception is high-speed connectors dedicated to that IC (e.g. motherboard connectors).

When a product is finally assembled, flexible wires and cables inside may lie in a variety of positions. Ensure that no wires or cables can lie near any high-speed devices. (Products without internal wires or cables are usually easier to make EMC compliant anyway.)

A heat-sink is an example of a conductor, and clearly can’t be located a long way away from the IC it is to be cooling. But heat-sinks can suffer from coupled signals from inside an IC just like any other conductor. The usual technique is to isolate the heat-sink from the IC with a thermal conductor (the thicker the better as long as thermal dissipation targets are met), then ‘ground’ the heat-sink to the local ground plane with many very short connections (the mechanical fixings can often be used).


  • A good quality watchdog that ‘keeps on barking’ is required.

Interference often occurs in bursts lasting for tens or hundreds of milliseconds. A watchdog which is supposed to restart a processor will be no good if it allows the processor to be crashed or hung permanently by later parts of the same burst that first triggered the watchdog. So it is best if the watchdog is an astable (not a mono-stable) that will keep on timing out and resetting the microprocessor until it detects a successful reboot. (Don’t forget that the watchdog’s timeout period must be longer than the processor’s rebooting time.)

AC-coupling of the watchdog input from a programmable port on the micro helps ensure reliable watchdog operation. For more on watchdogs, see section 7.2.3 in [1].


  • An accurate power monitor is needed (sometimes called a ‘brownout’ monitor).

Power supply dips, drop-outs interruptions, sags, and brownouts can make the logic’s DC rail drop below the voltage required for the correct operation of logic ICs, leading to incorrect functioning and sometimes over-writing areas of memory with corrupt instructions or data. So an accurate power monitor is required to protect memory and prevent erroneous control activity. Simple resistor-capacitor ‘power-on reset’ circuits are almost certainly inadequate.


  • Never use programmable watchdogs or brownout monitors.

Because programmable devices can have their programs corrupted by interference, programmable devices must not be used for watchdog or power monitor functions.


  • Appropriate circuit and software techniques also required for power monitors and watchdogs so that they cope with most eventualities, depending on the criticality of the product, (not discussed further in this series of articles).




  • High quality RF bypassing (decoupling) of power supplies is vital at every power or reference voltage pin of an IC (refer to Part 5 of this series).




  • High quality RF reference potential and return-current planes (usually abbreviated to ‘ground planes’) are needed for all digital circuits (refer to Part 5 of this series).




  • Use transmission line techniques wherever the rise/fall time of the logic signal edge is shorter than the “round trip time” of the signal in the PCB track (transmission lines are described in detail in the 5th article in this series).

Rule of thumb: round trip time equals 13ps for every millimeter of track length. For best EMC it may be necessary to use transmission line techniques for tracks which are even shorter than this rule of thumb suggests.


  • Asynchronous processing is preferred.

Asynchronous (naturally clocked) techniques have much lower emissions than synchronous logic, and much lower power consumption too. ARM has been developing asynchronous processors for many years, and other manufacturers are now beginning to produce asynchronous products.

One of the limitations on designing asynchronous ICs was the lack of suitable design tools (e.g. timing analyzers). But at least one asynchronous IC design tool is now commercially available.


Some digital ICs emit high level fields from their own bodies, and often benefit from being shielded by their own little metal box soldered to the PCB ground plane. Shielding at PCB level is very low-cost, but can’t always be applied to devices that run hot and need free air circulation.


Clock circuits are usually the worst offenders for emissions, and their PCB tracks will be the most critical nets on a PCB, requiring component layout to be adjusted to minimize clock track length and keep each clock track on one layer with no via holes.


When a clock must travel a long distance to a number of loads, fit a clock buffer near the loads so the long track (or wire) has smaller currents in it. Where relative skew is not a problem clock edges in the long track should be well-rounded, even sine-waves, squared up by the buffer near the loads.


1.1.5 Spread-spectrum clocking

So-called "spread-spectrum clocking" is a recent technique that reduces the measured emissions, although it doesn't actually reduce the instantaneous emitted power so could still cause the same levels of interference with some fast-responding devices. It modulates the clock frequency by 1 or 2% to spread the harmonics and give a lower peak measurement on CISPR16 or FCC emissions tests. The reduction in measured emissions relies upon the bandwidths and integration time constants of the test receivers, so is a bit of a trick, but has been accepted by the FCC and is in common use in the US and EU. The modulation rates in the audio band so as not to compromise clock squareness specifications.


Figure 2 shows an example of an emission improvement for one clock harmonic.

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