Volume I section administrative items cover Sheet




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Figure 2.15-3. RPI 8-inch wafer Class 100/10 Clean Room (one bay) and (right) Alcatel 200 ICP Deep Trench Etcher (3D vertical high aspect ratio via cross sectional SEM photograph.)


The equipment obtained during the DARPA/MARCO iFRC funding of 3D research at RPI includes the EVG Smart View aligner and bonder systems.





Figure 2.15-4. RPI EVG SmartView 3D Aligner and Wafer Bonder for 8 inch wafers





Figure 2.15-5. Karl Suss Probe Station 2000 automated full wafer prober.

2.16 References


[1] G. Moore, “Cramming more components onto Integrated Circuits,“ Electronics, Vol 38, pp. 114-117, April 19, 1965.

[2] R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, andA.R. LeBlanc, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, Oct. 1974.

[3] H. B. Bakoglu and J. D. Meindl, "Optimal interconnection circuits for VLSI," IEEE Trans. Electron Dev., vol. ED-32, pp. 903-909, May 1985.

[4] K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, A. Young, “Interconnects in the Third Dimension: Design Challenges for 3D ICs,” 44th Design Automation Conference, 2007, pp. 562-567.

[5] J. Hennessy and D. Patterson, “Computer Architecture: A Quantitative Approach,” 3rd, Elsevier, Jan. 2003.

[6] Amdahl, G.M., "Validity of the single-processor approach to achieving large scale computing capabilities," Proceedings of AFIPS Conference, 1967, pp. 483-485.

[7] Krishnaprasad, S., “Uses and Abuses of Amdahl’s Law,” Proc. CCSC: Southeastern Conference, reprinted in JCSC 17(#2), Dec. 2001, pp. 288-293.

[8] O'Neal, David, "On Microprocessors, Memory Hierarchies and Amdahl's Law," Carnegie Mellon University, Pittsburgh Supercomputing Center, Pittsburgh, PA. See web link http://archive.ncsa.uiuc.edu/EP/CSM/presentations, November 1999.

[9] P. Jacob, A. Zia, J.F. McDonald, and R.P. Kraft, “Predicting the Performance of a 3D Processor-Memory Chip Stack,” IEEE Design & Test of Computers, Vol. 22, No. 6, pp. 540-547, Nov. 2005.

[10] Jacob, P., Zia, A., Erdogan, O., Belemjian, P. M. Kim, J.-W., Chu, M., Kraft, R.P.,

McDonald, J. F., and Bernstein, K., “Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks” Proceedings of the IEEE,, Sp. Issue on 3D Electronics, Vol. 97, No. 1, January 2009 pp. 109-122.

[11] Emma, P.G., “How Bandwidth Works in Computers,” Chapter 11 in High Performance Energy Efficient Microprocessor Design, edited by V.G. Oklobdzija and R. Krishnamurthy, published by Springer, Feb., 2006.

[12] P. Pujare, and A. Aggarwal, “Cache Noise Prediction,” IEEE Trans. on Computers, , 57(#10), October 2008, pp;. 1372-1384.

[13] J. Edler, M.D. Hill, “Dinero IV: Trace-Driven Uni-processor cache simulator”

http://www.cs.wisc.edu/~markhill/DineroIV/

[14] C.J. Hughes, V.S. Pai , P. Ranganathan ,S.V. Adve , “RSIM: simulating shared memory multiprocessors with ILP processors”, Feb 2002, vol. 35, Issue: 2, pp.40.

[15] R. Fernandez , J. M.García. RSIM x86: A cost-effective performance simulator. In 19th European Conference on Modelling and Simulation, June 2005, pp 774-779.

[16] T. H. Ning, P. M. Solomon and D. D. Tang, Scaling properties of Bipolar Devices, Electron Devices Meeting, 1980 International Volume 26, Issue , 1980 Page(s): 61 - 64

[17] P. M. Belemjian, O. Erdogan, R. P. Kraft, and J. F. McDonald, "SiGe HBT Microprocessor Core Test Vehicle," Proc. IEEE [Special Issue on SiGe Technology Guest Editors, R. Singh, D. Harame, and B. Meyerson], Vol. 93(#9), Sept. 2005, pp. 1669-1678.

[18] H. J. Greub, J. F, McDonald, T. Yamaguchi, and T. Creedon), "Cell Library for Current Mode Logic using an Advanced Bipolar Process," (with H. J. Greub, T. Yamaguchi, and T. Creedon), I.E.E.E. J. Sol. State Cir., Special issue on VLSI, (D. Bouldin, guest editor), I.E.E.E. Trans. on Solid State Circuits, Vol. JSSC-26 (#5), pp. 749-762, May, 1991.

[19] C. L., Ratzlaff and L. T. Pillage, "RICE: Rapid Interconnect Circuit Evaluation Using AWE" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 6, June 1994, pages 763--776.

[20] Bard, K.; Dewey, B.; Hsu, M.-T.; Mitchell, T.; Moody, K.; Rao, V.; Rose, R.; Soreff, J.; Washburn, S., Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM.
 Proceedings of the IEEE,
 Volume 95, Issue 3, March 2007 Page(s):530 – 554.

[21] Hill, M. D. and Murty, M. R. “Amdahl’s Law in the Multicore Era,” http://www.cs.wisc.edu/multifacet/papers/tr1593_amdahl_multicore.pdf

[22] J.A. Kahl, M.N. Day, H.P. Hofstee, C.R. Johns, T.R. Maeurer, and D. Shippy. Introduction to the Cell Multiprocessor. IBM Journal of Research and Development, 49(4), 2005.

[23] Morad, T. Y. Weiser, U. C. Kolodny, A. Valero, M. Ayguadé, E., “Performance, Power

Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors,” IEEE Computer Architecture Letters [1556- 6056] Morad yr:2006 vol:5 iss:1 pg:14.

[24] D. Moncrieff, R. E. Overill, and S. Wilson. “Heterogeneous Computing Machines and Amdahl's

Law.” Parallel Computing, vol. 22, 1996.

[25] F. Pollack. "New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies." Micro 32, 1999,

http://www.intel.com/research/mrl/Library/micro32Keynote.pdf

[26] Y. Taur, and T. H,. Ning, “Fundamentals of Modern VLSI Devices,” Cambridge University

Press, 2001.

[27] Q. Chen, D. Zhang, Z. Xu, A. Beece, R.Patti, Z. Tan, Z.Wang, L. Liu, and J.-. Lu , “A novel

chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment,” Microelectronic Engineering, electronic Journal homepage: www.elsevier .com/ locate/mee.


2.17 Selected PI Papers for Background and Expertise Evaluation





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