Volume I section administrative items cover Sheet




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James Jian-Qiang Lu


Department of Electrical, Computer and Systems Engineering

Center for Integrated Electronics (CIE)

Rensselaer Polytechnic Institute, Troy, NY 12180-3590, USA

Tel: (518) 276-2909; E-mail: luj@rpi.edu; http://www.rpi.edu/~luj


Professional Preparation:

12/1995 Ph.D. (Dr. rer. nat), Technical University of Munich, Germany

06/1986 M.S., Beijing Normal University, China

06/1983 B.S., Shanxi Normal University, China


PROFESSIONAL EXPERIENCE:

07/07 - present Associate Professor, Rensselaer Polytechnic Institute, Troy, NY

07/02 - 06/07 Associate Research Professor, Rensselaer Polytechnic Institute, Troy, NY

08/99 - 06/02 Assistant Research Professor, Rensselaer Polytechnic Institute, Troy, NY

04/97 - 07/99 Research Scientist, Rensselaer Polytechnic Institute, Troy, NY

02/96 - 03/97 Research Associate, University of Virginia, Charlottesville, VA

10/92 - 02/96 SIEMENS Scholar, Research Scientist, Technical University of Munich, Germany

11/90 - 09/92 DAAD Scholar, Technical University of Munich, Germany

07/86 - 05/90 Section Director/ Lecturer, Beijing University of Posts and Telecommunications, China


Publications: Authored/co-authored more than 200 publications in refereed journals, conferences or books, and given many invited presentations or keynotes; >150 papers on 3D integration/packaging.


PUBLICATIONS MOST RELEVANT TO PROPOSED RESEARCH:

  1. J.-Q. Lu, “3D Hyper-Integration and Packaging Technologies for Micro-Nano-Systems”, (Invited) Proceedings of the IEEE, 97 (1), pp. 18-30, January 2009.

  2. Z. Xu and J.-Q. Lu, “High-Speed Design and Broadband Modeling of Through-Strata-Vias (TSVs) in 3D Integration”, IEEE Transactions on Advanced Packaging (in press).

  3. Q. Chen, D. Zhang, Z. Xu, A. Beece, R. Patti, Z. Tan, Z. Wang, L. Liu, and J.-Q. Lu, “A Novel Chip-to-Wafer (C2W) Three-dimensional (3D) Integration Approach Using a Template for Precise Alignment”, Microelectronic Engineering (in press).

  4. J.-Q. Lu, T.S. Cale and R.J. Gutmann, “Polymer Adhesive Bonding Technology”, book chapter in “Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits,” Eds. P. Garrou, C. Bower, and P. Ramm, Vol. 1, pp. 249-259, Wiley-VCN, May 2008.

  5. J.-Q. Lu, J.J. McMahon1, and R.J. Gutmann, “3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer-Level Bonding Interfaces”, (Invited) in Materials and Technologies for 3 D Integration, pp.69-80, MRS. Vol. 1112, 2008.

OTHER PUBLICATIONS:

  1. Z. Liu, L. Ci, S. Kar, P.M. Ajayan, and J.-Q. Lu, “Fabrication and Electrical Characterization of Densified Carbon Nanotube Micro-Pillars for IC Interconnection”, IEEE Transactions on Nanotechnology, Vol. 8, No. 2, pp. 196-203, March 2009.

  2. J.-Q. Lu, T.S. Cale and R.J. Gutmann, “3D Integration Based upon Dielectric Adhesive Bonding”, Chapter 10 in "Wafer Level 3-D ICs Process Technology", Eds., C.S. Tan, R.J. Gutmann, and R. Reif, pp. 219-256. Springer, 2008.

  3. J.-Q. Lu, K. Rose, and S. Vitkavage, “3D Integration: Why, What, Who, When?” Future Fab International, Vol. 23, pp. 25-27, July 2007.

  4. F. Niklaus, J.-Q. Lu, G. Stemme, and R. Gutmann, “Adhesive Wafer Bonding”, Journal of Applied Physics (Applied Physics Review – Focused Review), Vol. 99, p. 031101 (2006).


Synergistic Activities:

Pioneer in the research of three-dimensional (3D) hyper-integration, including 3D integration architecture and platforms, processing and fabrication, design, simulation and applications. Research publications covering from micro-nano-electronics theory and design to materials, processing, devices, integration and packaging, including GaAs devices and lateral injection ridge laser, GaN LEDs and power devices, Si bipolar device and MOSFETs, novel 3D FETs, terahertz electronics, Si IC and advanced packaging.

Conference Committee Members: IEEE International Electron Devices Meeting (IEDM); IEEE International 3D System Integration Conference (3DIC); IEEE International Interconnect Technology Conference (IITC); IEEE Electronic Components and Technology Conference (ECTC); SEMI/IEEE Advanced Semiconductor Manufacturing Conf. (ASMC); Intern’l Conference on Device Packaging; IMAPS Intern’l Symposium on Microelectronics; TMS Electronic Materials Conference (EMC), etc.


Chair/Session Chair: Technical Chair of IMAPS Intern’l Conference on Device Packaging; Chair of IMAPS-3D Packaging Workshop; Session Chairs for IEEE Intern’l 3D System Integration Conference (3D IC); IEEE Electronic Components and Technology Conference (ECTC); IEEE International Electron Devices Meeting (IEDM); SEMATECH Workshop on Thermal and Design Issues in 3D-ICs; Intern’l VLSI Multilevel Interconnection (VMIC) Conferences; Intern’l Workshop on Wafer Bonding for MEMS Technologies; and IMAPS Intern’l Symposium on Microelectronics.



Recent Awards:School of Engineering Research Excellence Award” at RPI in 2005; “IEEE CPMT Exceptional Technical Achievement Award” in 2008 and “William D. Ashman Achievement Award from International Microelectronics And Packaging Society (IMAPS)” in 2010.


Collaborators & Other Affiliations:

  • Recent Collaborators and Co-Editors: Prof. P. Ajayan (Rice University), Dr. S. Arkalgud (SEMATECH), Prof. I. Bhat (RPI), Dr. K.-N. Chen (National Chiao Tung University, Taiwan), Dr. S. Chickamenahalli (Intel), Prof. P. Chow (RPI), Prof. Y. Danon (RPI), Prof. T.A. Fjeldly (Norwegian Univ. of Sci., & Tech.), Prof. R. Karlicek (RPI), Dr. Kevin Gu (IBM), Prof. R.J. Gutmann (RPI), Dr. W. Haensch (IBM), Prof. R. Huang (RPI). Dr. R. Jones (Freescale), Dr. R. Kumar (Intel), Prof. A.E. Kaloyeros (Univ. at Albany), Prof. L. Liu (Tsinghua University), Prof. T.-M. Lu (RPI), Prof. J. McDonald (RPI), Prof. F. Niklaus (Royal Institute of Technology, Sweden), Dr. Peter Ramm (Fraunhofer), Prof. R. Reif (MIT), Prof. K. Rose (RPI), Prof. M.S. Shur (RPI), Prof. J. Sun (RPI), Prof. G.-C. Wang (RPI), Prof. Z. Wang (Tsinghua University), Dr. A. Young (IBM), Dr. K. Yu (Freescale), Prof. T. Zhang (RPI).

3D Packaging Chair, National Technical Committee of IMAPS Society since 2005

  • Professional Affiliations

Fellow, IEEE (Institute of Electrical and Electronics Engineer)

Fellow and Life Member, International Microelectronics And Packaging Society (IMAPS)

Member, Materials Research Society (MRS), American Physical Society (APS)

  • Graduate Advisors

Ph.D advisor: Prof. F. Koch (Technical University of Munich, Germany); M.S. advisor: Prof. Z.L. Wang (Peking University, China);

  • Thesis Advisor and Postgraduate-Scholar Sponsor

Total graduate students advised or co-advised: 20, including C. Berry (IBM), A. Faisal (IBM), T.J. Hwang (Samsung), Y. Kwon (Samsung), J.J. McMahon (GE), D. Notaro (GT Solar), J. Yu (IBM).

Total postgraduate-scholar sponsored: 17, including S.H. Lee (University Research Foundation), A. Jindal (Micron), R. Kumar (Intel), Y. Kwon (Samsung), K. Lee (Samsung), H.-f. Li (Freescale Semiconductor), F. Niklaus (Royal Institute of Technology (KTH).

Citizenship: U.S.A.


2.9-1. Table of Time Commitments


This is a university research proposal. Some fraction of professorial time (20-30%) is always devoted to research whether sponsored or not, and their role as charged to a contract or grant is one of mentor, adviser, and administrator, whilst most actual research activity is conducted by doctoral students. Release time on the order of 4-5% per award provides release time from other activities such as service on committees or teaching extra courses. In addition some aspects of the proposed work enjoy current sponsorship on related subject matter (some is due to run out during the proposed period of performance). Because the students that may be involved will be hired at the time of any award it is not possible to name any of them. In addition, the subcontract through MOSIS to IBM for 9HP involves sponsorship of a new and emerging technology the fee for which doubtless contains process development hours at IBM. Hence the table of key individual time commitments is tabularized as follows:


Key

Individual

Project

Pending/Current

2011

2012

2013

Graduate

Student 1

Design/3D

Fabrication

This Proposal

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

Graduate

Student 2

Design/3D

Fabrication

This Proposal

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

Graduate

Student 3

Design/3D

Fabrication

This Proposal

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

Graduate

Student 4

Design/3D

Fabrication

This Proposal

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

720AY+480SU

=1200 hours

John

McDonald

NSF EAGER

Current

5% AY, 1 wk, summer

N/A

N/A

John McDonald

NRO 80Gb/s

SiGe HBT

Current

5% AY, 1 wk, summer

N/A

N/A

John

McDonald

NRL SiGe HBT

Current

0% AY, 0 wk,

summer

N/A

N/A

John

McDonald

NRO DII 120Gb/s

Proposed

5% AY, 1 wk,

summer

N/A

N/A

John

McDonald

DARPA OHPC

This Proposal

6%AY (86.4 hours), 4 wk, summer (120 hours)

6%AY (86.4 hours), 4 wk, summer (120 hours)

6%AY (86.4 hours), 4 wk, summer (120 hours)

James Lu

DARPA OHPC

This Proposal

6%AY (86.4 hours), 4 wk, summer (120 hours)

6%AY (86.4 hours), 4 wk, summer (120 hours)

6%AY (86.4 hours), 4 wk, summer (120 hours)


One reason for mentioning the NSF EAGER award is that it can if it renews beyond 2011, it could then provide perhaps two more students to support this work, but of course that renewal is not a certainty. This EAGER, prior DARPA HPCS, and DARPA 3DIC funding, along with a DARPA seedling a few years back sponsored by Mike Fritze, provided much of the background for this proposal.

Note that because most of the work is done at RPI, and graduate student support is available only for fixed tuition and stipend as a unit, the fund consumption rate of the effort will be nearly constant except for the final 9HP fabrication in the third year, 2013, when the first 9HP runs will start.


2.10 Conflict of Interest


There are no conflicts of interest. However, wafers to be fabricated at IBM will their design kits for their 9HP and 32SO1 processes.


2.11 Human Use


There is no Human use for experimentation.


2.12 Animal Use


There is no Animal use for experimentation.


2.13 Statement of Unique Capability for FFRDC


While there is collaboration with Lincoln Labs and SEMATECH it is informal and not contractual.


2.14 Government funded Team Member Eligibility


There are no government funded team members, only informal collaborators..


2.15 Facilities:


The proposed work requires both design and fabrication activities. Early work will require an assortment of workstations and computational facilities some of which are shown in Figure 2.15-1.





Figure 2.15-1. Various Computational tools for use in the proposed design work, including workstations, research servers, and an IBM Blue Gene Supercomputer.


As a result of prior DARPA and other sponsorship excellent testing instrumentation is available up to 40 GHz or more. This includes oscilloscopes to 50 GHz, signal generators up to 40 GHz and spectrum analyzers to 40 GHz.





Figure 2.15-2. Instrumentation and die/wafer probes to 40 GHz or higher.


RPI has been a DARPA/MARCO pioneer in developing fabrication capability for 3D by wafer to wafer bonding. Numerous papers have been published on this subject by the RPI team. For the 3D Wafer Fabrication part of the project RPI is probably one of 3 universities that have attained a full wafer to wafer bonding capability assembled in an 8,000 foot 8-inch wafer class 100/10 clean room.


The equipment obtained during the DARPA/MARCO iFRC funding of 3D research at RPI includes the EVG Smart View aligner and bonder systems shown below in Figure 2.15-3.




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