Scheme of examination & syllabi for Master of Technology




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SCHEME OF EXAMINATION


&


SYLLABI


for


Master of Technology
(VLSI Design)

Regular










Guru Gobind Singh Indraprastha University

Kashmere Gate, Delhi – 110403 [INDIA]

www.ipu.ac.in

Eligibility Condition


B. Tech / B.E in Electronics & Communication / Electronics / Computer Science / Information Technology or equivalent degree with 60% marks.


M Sc. Physics (Electronics) / M Sc. Electronics with 60% marks.


Admission Procedure


Admission will be made on the basis of GATE score in the relevant field.


If seats remain vacant after admitting the students with valid GATE score, then the admission will be made on the basis of merit of the qualifying marks subject to minimum 60% marks in the qualifying degree.


SCHEME OF EXAMINATION


Master of Technology

(VLSI Design)


First Semester


Course

Code

Subject Name

L

T/P

Credits

Theory Papers

ITV-601

Digital System Design with Verilog

4

-

4

ITV-603

VLSI Technology

4

-

4

ITV-605

Basic VLSI Design

4

-

4

ITR-601

Algorithm Analysis and Design

4

-

4

ITR-605

Advance Computer Architecture

4

-

4

Practical /Viva-voce

ITV-651

DSD with Verilog Lab

-

2

2

ITV-653

Digital IC design Lab

-

2

2

ITV-655

AAD Lab

-

2

2

Total

20

8

26
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