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Front End Processes
The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment.
Table of Contents
Front End Processes 1
2Difficult Challenges 2
2.1The Future of MOSFET – New Materials and New Structures 2
3Technology Requirements and Potential Solutions 4
3.1Logic Devices – High Performance (HP), Low Operating Power (LOP),
and Low Standby Power (LSTP) 4
3.2DRAM Devices 6
3.3Non-volatile Memory (Flash) 7
3.43D Flash Memory 14
3.5Phase Change Memory 16
3.6Ferroelectric Random Access Memory (FeRAM) 19
3.7Starting Materials 21
3.8Front End Surface Preparation 27
3.9Thermal/Thin FILMS and Doping 31
3.10Doping Technology 34
3.11Front End Etch Processing 38
3.12Shallow Trench Isolation Chemical-mechanical Planarization (STI CMP) 42
4Cross-Cut Issues 45
5Inter-Focus ITWG Discussion 45
6Impact of Future Emerging Research Devices 45
6.1FEP Metrology Cross-Cut Issues 46
6.2FEP Modeling and Simulation Cross-Cut Issues 46
6.3FEP Environment, Safety, and Health Cross-Cut Issues 47
List of Figures
List of Tables
Table FEP1 Front End Processes Difficult Challenges 2
Table FEP2 High Performance Device Technical Requirements 2
Table FEP3 Low Operating Power Device Technical Requirements 2
Table FEP4 Low Standby Power Devices Technical Requirements 2
Table FEP5 DRAM Stacked Capacitor Technology Requirements 6
Table FEP6 Floating Gate FLASH Non-volatile Memory Technology Requirements 8
Table FEP7 Charge Trapping FLASH Non-volatile Memory Technology Requirements 13
Table FEP8 Phase Change Memory (PCM) Technology Requirements 18
Table FEP9 FeRAM Technology Requirements 19
Table FEP10 Starting Materials Technology Requirements 21
Table FEP11 Surface Preparation Technology Requirements 27
Link to Table FEP11. 29
Table FEP12 Thermal, Thin Film, Doping Process Technology Requirements 31
Table FEP13 Etching Process Technology Requirements 38
Table FEP14 STI CMP Process Technology Requirements 43
Front End Processes
The Front End Processes (FEP) Roadmap focuses on future process requirements and potential solutions related to scaled field effect transistors (MOSFETs), DRAM storage capacitors, and non-volatile memory (Flash, Phase-change, and ferroelectric). The purpose of this chapter is to define comprehensive future requirements and potential solutions for the key front end wafer fabrication process technologies and the materials associated with these devices. Hence, this Roadmap encompasses the tools, and materials, as well as the unit and integrated processes starting with the wafer substrate and extending through the contact silicidation processes and the deposition of strain layers (pre-metal dielectric deposition and contact etching is covered in the Interconnect chapter). The following specific technology areas are covered: logic devices, including high performance, low operating power, and low stand-by power; memory devices, including DRAM, flash, phase-change, and FeRAM; starting materials; surface preparation; thermal/thin films/doping; plasma etch; and CMP.
A forecast of scaling-driven technology requirements and potential solutions is provided for each technology area. The forecasted requirements tables are model-based unless otherwise noted. The identified potential solutions serve to benchmark known examples of possible solutions, and are intended for other researchers and interested parties. They are not to be considered the only approaches. Indeed, innovative, novel solutions are sought, and their need is identified by red colored regions of the requirements tables.
Some FEP-related topics are presented in other sections of this Roadmap. The scaled device performance and structures forecasts that drive FEP requirements are covered in the Process Integration, Devices, and Structures (PIDS) chapter. The crosscut needs of FEP are covered in the following chapters: Yield Enhancement; Metrology; Environment, Safety, & Health; and Modeling & Simulation. FEP factory requirements are covered in the Factory Integration chapter.
Figure FEP1 Front End Process Chapter Scope
MOSFET scaling has been the primary means by which the semiconductor industry has achieved the historically unprecedented gains in productivity and performance quantified by Moore’s Law. These gains have traditionally been paced by the development of new lithography tools, masks, photoresist materials, and critical dimension etch processes. In the past several years it has become clear that despite advances in these crucial process technologies and the resultant ability to produce ever-smaller feature sizes, front end process technologies have not kept pace, and scaled device performance has been compromised primarily due to unacceptable leakage/power delivered by sheer geometric scaling. To stay on the performance at low power curve, new materials have now been put into production for transistor gate stack fabrication. Non-planar multi-gate devices have been announced as new approaches to device structure, and within the next several years we expect to see the introduction of additional approaches, as well as new materials to increase channel mobility as well as.
Material-limited device scaling has placed new demands on virtually every front end material and unit process, starting with the silicon wafer substrate and encompassing the fundamental planar CMOS building blocks and memory storage structures. In addition, the end of planar bulk CMOS is becoming visible within the next several years. As a consequence we must be prepared for the emergence of CMOS technology that uses non-conventional MOSFETs or alternatives such as planar FDSOI devices and dual- or multi-gate devices of vertical geometry. An overview of the device alternatives is presented in the Emerging Research Devices chapter. Projections for the manufacturing introduction of non-conventional MOSFET devices are 2013-2015 for FDSOI and/or multi-gate. The challenges associated with integration of these diverse new materials and structures are the central theme of the FEP difficult challenges summarized in Table FEP1.
Table FEP1 Front End Processes Difficult Challenges
High- gate dielectric with metal gate electrode is now used in production but continued scaling of equivalent oxide thickness (EOT) below 0.6 nm while preserving electrical performance and reliability will be a challenge. Channel strain engineering to increase mobility was introduced to manufacturing several years ago and has become an integral part of MOSFET transistor scaling now and is expected to continue in the near future. Continued improvement in strain engineering and application to new device structures is identified as an FEP difficult challenge.
Continued transistor performance at low power scaling is expected to require the replacement of planar CMOS devices with non-classical devices which includes fully depleted planar and non-planar devices in our analysis. The transition from extended bulk CMOS to non-classical device structures is not expected to take place at the same time for all applications and all chip manufacturers. Instead, a scenario is envisioned where a greater diversity of technologies are competitively used at the same point in time—some manufacturers choosing to make the transition to non-classical devices earlier, while others emphasize extensions of bulk technology. This is reflected in the High-Performance and Low-Power Device Technology Requirements Tables FEP2, FEP3 and FEP4, by the projection of requirements for multiple approaches in the transition years from 2013 through 2019.
Table FEP2 High Performance Device Technical Requirements
Table FEP3 Low Operating Power Device Technical Requirements
Table FEP4 Low Standby Power Devices Technical Requirements
The introduction of new materials is also expected to necessitate new techniques to dope and activate silicon. Series resistance is critical in the near term and needs to be addressed to achieve the goals through 2015. It should be noted that series resistance becomes even more critical when alternate device options [FDSOI, multi-gate] are considered. In addition to the scaling imposed need for producing very shallow highly activated junctions, the limited thermal stability of most high-mobility materials is expected to place new boundaries on thermal budgets associated with dopant activation. In a worst-case scenario, the introduction of these materials could have a significant impact on the overall CMOS process architecture.
In the memory area, stand-alone DRAM device manufacturing has narrowed to the stacked capacitor approach. Therefore, the Technology Requirements table and text for DRAM trench capacitor has been removed and the DRAM section is implicitly aimed at stacked capacitor technologies alone. The DRAM tables were still in review and not changed for 2011, but will be addressed and updated in 2012. Note that much of the scaling effort in DRAMs continues along the pathways currently shown in the current ITRS tables. High-materials are now in production for DRAM capacitors using metal-insulator-metal (MIM) structures. It is expected that high-materials will be required for the floating gate Flash memory interpoly dielectric by 2012 and for tunnel dielectric by 2013. FeRAM will make a commercial appearance where ferroelectric and ferromagnetic storage materials would be used. The introduction of these diverse materials into the manufacturing mainstream is viewed as important difficult challenges. Phase-change memory (PCM) devices are in commercial production, although not in wide usage.
In starting materials, it is expected that bulk silicon will continue to dominate, but alternative silicon-on-insulator (SOI) substrates, will find increasing usage was well, particularly for special product application. Such bulk alternatives generally imply process architecture changes that impact FEP. Various and complementary forms of strained silicon technology have been adopted for high performance designs and continue to be principally achieved through value-added modifications to the IC manufacturing process. Also, an important difficult challenge within the 2011 Roadmap horizon is the need for the next generation 450 mm silicon substrate. Such a diameter move is driven by the need to maintain pace with historic productivity enhancements based on augmented transistor count performance gains. There are concerns whether the incumbent techniques for substrate production can be cost-effectively scaled to the next generation. There are indications that mere scaling of present techniques alone, in certain cases, will not be sufficient. It is also uncertain whether this substrate will be bulk silicon, SOI or perhaps include both types. While strain remains an important performance booster, it appears that these benefits will continue to be derived via integration within the device process. There is some consideration within the roadmap horizon that the device channels may be non-silicon but a general consensus still exists that the substrate will continue to be silicon. Therefore, an important research need is the development of an understanding of new material interaction with silicon. Also, based upon historical diameter change cycles, the industry is already several years behind the pace necessary to allow the next generation 450 mm silicon substrate to be ready for device manufacture in the year 2014, although the pace of advancement in 2010 / 2011 has seemingly accelerated appreciably.
Front end cleaning processes will continue to be impacted by the introduction of new front end materials such as higher dielectrics, metal gate electrodes, and mobility-enhanced channel materials. Scaled devices are expected to become increasingly shallow, requiring that cleaning processes become completely benign in terms of substrate material removal and surface roughening. Scaled and new device structures will also become increasingly fragile, limiting the physical aggressiveness of the cleaning processes that may be employed. In addition, these new device structures will require precise cleaning and characterization of vertical surfaces. DRAM storage capacitor structures will show increasing aspect ratios making sidewall contamination removal increasingly difficult. Also, there is a challenge for particle scanning technology to reliably detect particles smaller than 28 nm on a wafer surface for characterization of killer defect density and to enable yield learning.
The gate dielectric has emerged as one of the most difficult challenges for future device scaling. Long-term scaling of high-κ stacks below 0.6 nm EOT remains a major challenge. The gate electrode also represents a major challenge for future scaling, where work function, resistivity, and compatibility with CMOS technology are key parameters for the new candidate gate electrode materials especially when the industry introduces new device architectures (fully depleted SOI or non-planar devices) to maintain electrostatic control and curtail the leakage current while scaling Lg. Another very difficult challenge in device scaling is channel mobility enhancement, making mechanical stress a first-order consideration in the choice of front end materials and processes. In order to maintain high device drive currents, technology improvements are required to increase channel mobility of traditional bulk CMOS devices, as well as partially depleted-, and fully depleted SOI devices, and non-planar devices. It is expected (based on a survey conducted by PIDS) that high mobility channels based on III-V (In-Ga-As) and Ge will replace Si channels for n and pFETs around 2018. The selective incorporation of these high mobility channels on Si in a VLSI scheme is a clear challenge.
Additional challenges include continued scaling and abruptness of shallow junctions, parasitic and contact resistance. Variability in the placement of dopant atoms and their final location, along with variations resulting from process control introduced by patterning, cleaning and deposition constitute a dominant scaling challenge, requiring considerable effort in developing new variability tolerant process techniques.. These challenges and potential solutions are discussed in more details under the Thermal, Thin Films, and Doping Processes section of this chapter.
The persistent challenge in scaling device sizes is the control of gate length critical dimensions (CD). Etching uniformity all the way to the wafer edge is a particularly difficult issue,and requires significant design fixes to improve manufacturability. As gate CD shrinks, the presence of line width roughness (LWR) is becoming the biggest portion of CD variation at 28nm technology node and beyond. The LWR is at best staying constant as the line width shrinks, which makes it a major scaling concern. Current methods of quantification need to be standardized to allow the industry to address the problem. The choice of photoresist type, etch bias power, and etch chemistry are critical for keeping low LWR. With high-κ dielectrics and metal gates in production, etch processes with sufficient selectivity and damage control for use with these materials have been identified. As non-planar transistors become necessary, dry etch becomes much more challenging. FinFET configurations bring new constraints to selectivity, anisotropy, and damage control.
Chemical-Mechanical Planarization (CMP) is becoming more important for Front End Processing. Being a critical step in the formation of shallow trench isolation for many nodes, its need and uniformity control has become even more important in flash memory devices and in the implementation of gate-last metal gate integration schemes. Uniformity, selectivity, and pattern density dependency continue to be challenges for CMP processes.
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