Emerging Research Devices




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International
Technology Roadmap
for
Semiconductors


2005 Edition


Emerging Research Devices


The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment.

Table of Contents

Scope 59

Difficult Challenges 59

Introduction 59

Device Technologies 60

Materials Technologies 61

Nano-information Processing Taxonomy 62

Emerging Research Devices 63

Memory Devices 63

Introduction 63

Memory Taxonomy 64

Memory Devices—Definition and Discussion of Table Entries 70

Logic Devices 72

Introduction 72

Logic Devices—Definition and Discussion of Table Entries 76

Emerging Research Materials 81

Introduction 81

Critical Properties 81

1D Charge State Materials 83

Key Challenge 83

Growth with Controlled Properties and Location 83

Nanotube Purification and Directed Assembly 84

1D Charge State Material Interfaces 84

Critical Metrology for Carbon Nanotubes 85

Molecular State Materials 85

Key Challenge 85

Introduction 85

Transport and IV Non-linearity 85

Bi-stable States 86

Molecular State Contacts 86

Metrology 86

Spin State Materials 86

Key Challenges 86

Introduction 86

Ferromagnetic Semiconductor Devices 87

Spin Injection Materials 87

Strongly Correlated Electron State Materials 88

Background 88

Definitions 88

Key Challenge 88

Material Properties 88

Synthesis 89

Interface Materials 89

Characterization and Modeling 89

Material Synthesis 90

Introduction 90

Molecular Synthesis (Molecules and Macromolecules) 90

Thin Film Synthesis 90

Self and Directed Assembly 90

Contact Material Issues 91

Characterization 91

Introduction 91

3-Dimensional, Angstrom Resolution, Atomic Sensitivity (structure and composition) 91

Profiling of Local Properties 91

Metrology for Characterization of Band Structure and State Properties of Nanoscale Materials 92

Modeling and Simulation 92

Emerging Research Architectures 93

Introduction 93

Architectures—Definition and Discussion of Table Entries 94

Fine-Grained Parallel Implementations in Nanoscale Cellular Arrays 94

Reconfigurable Computers 95

Biologically Inspired Architecture Implementations 95

Coherent Quantum Computing 96

Trends 96

Emerging Technologies—A Functional Comparison 101

Introduction 101

Functional Parameterization and Comparison 101

Definition and Discussion of Table Entries 103

Emerging Technologies—A Critical Review 104

Introduction 104

Technologies beyond CMOS 105

Overall Technology Requirements 105

Charge-based Nanoscale Devices 106

Alternate Computational-State-Variable Nanoscale Devices 106

Potential Performance Assessment for Memory and Logic Devices 106

Relevance Criteria 106

Technology Performance Assessment 108

Fundamental Guiding Principles—“Beyond CMOS” Information Processing 116

Introduction 116

Guiding Principles 116

Computational State Variable(s) other than Solely Electron Charge 116

Non-thermal Equilibrium Systems 116

Novel Energy Transfer Interactions 116

Nanoscale Thermal Management 116

Sub-lithographic Manufacturing Process 116

References 117



List of Figures

List of Tables

Table 52 Difficult Challenges—Emerging Research Device Technologies 61

Table 53 Difficult Challenges—Emerging Research Materials Technologies 62

Table 54 Memory Taxonomy 65

Table 55 Current Baseline and Prototypical Memory Technologies 66

Table 56 Transition Table for Emerging Memory Devices 67

Table 57 Emerging Research Memory Devices—Demonstrated and Projected Parameters 68

Table 58 Transition Table for Emerging Logic Devices 73

Table 59 Emerging Research Logic Devices—Demonstrated Projected Parameters 74

Table 60 Critical Emerging Research Materials’ Properties 82

Table 61 Emerging Research Architecture Implementations 98

Table 62 Circuit and/or Architecture Implementations—Theory and Experiment 100

Table 63 Estimated Parameters for Emerging Research Devices and Technologies in the year 2016 103

Table 64 Performance Evaluation for
Emerging Research Memory Device Technologies (Potential) 108

Table 65 Performance Evaluation for
Emerging Research Logic Device Technologies (Potential) 108



Emerging Research Devices

Scope

The Semiconductor Industry is poised to sustain the extraordinary exponential growth of information technology for the next several years by continuing its unprecedented success in scaling CMOS beyond the 22 nm generation. Continued growth of information technology beyond ultimately scaled CMOS, in the nearer term, will require heterogeneous integration of new technologies with the CMOS platform, i.e., “enhanced CMOS.” In the longer term the industry is facing an exciting but daunting challenge to invent one or more fundamentally new approaches to information and signal processing. This will likely require discovery and exploitation a new means of physically representing, processing, storing and transporting information via new materials, process, device, nano-architecture, and systems innovations.

A primary goal of this chapter is to stimulate invention and research leading to one or more new concepts to extend functional scaling of information processing substantially beyond “ultimately scaled” CMOS. This goal is accomplished by addressing the two technology-defining domains identified above—extending the CMOS platform via heterogeneous integration of new technologies and, later, via developing new technological and nano-architectural concepts. The intent is two-fold. First is to “cast a broad net” to gather in one place substantive, alternative concepts for memory, logic, and information processing nano-architectures that would, if successful, substantially extend the Roadmap beyond CMOS. As such, this discussion will provide a window into these candidate approaches. Second is to provide a balanced, critical assessment of these emerging new device technologies for information processing. In this regard, a brief new section is added to propose a set of fundamental principles that will likely govern successful extension of information processing technology substantially beyond that attainable with ultimately scaled CMOS. This broadened chapter, therefore, provides an industry perspective on emerging new device technologies and serves as a bridge between bulk CMOS and the realm of microelectronics beyond the end of CMOS scaling.

In previous editions, the scope of this chapter included new approaches to emerging research memory, logic, and nano-architecture to enable new information processing technologies. For the 2005 ITRS, the scope is expanded to include an important new section on Emerging Research Materials. This section introduces and describes those properties of essential new materials critically required to support realization of the emerging research memory and logic devices. Additionally, this new materials section includes synthesis techniques, metrology and characterization and the modeling and simulation infrastructure and tools needed to develop those required materials. Conventional materials and processes currently used in CMOS technology, which may be also be used to realize Emerging Research Devices, will be treated in the Front End Processes (FEP) chapter. Also, the sub-section on Non-classical CMOS, previously treated in the 2003 ERD chapter, has been transferred to the Process Integration (PIDS) and FEP chapters. With this expanded scope, the chapter now addresses all physical technologies contributing to new information technology paradigm, from materials and devices to device level nano-architectures.

The discussion is divided into the following four categories: 1) Materials, 2) Memory Devices, 3) Logic Devices, and 4) information processing Nano-architectures. The discussions provide some detail regarding their operation principles, advantages, challenges, maturity, and current and projected performance. Also included is a preliminary but interesting comparison of the performance projections and cost attributes for several speculative new approaches to information and signal processing. An interesting observation of this comparison is that the emerging devices, materials, technologies, and architectures, given their successful development, would extend applications of microelectronics to domains not accessible to CMOS, rather than competing directly with CMOS in the same domain.

Finally, inclusion of a concept in this chapter does not in any way constitute advocacy or endorsement of that concept.

Difficult Challenges

Introduction

The microelectronics industry is facing two classes of difficult challenges related to extending integrated circuit technology beyond the maturation of CMOS scaling. One set relates to extending CMOS beyond its generic density and functionality by integrating, for example, a new high speed, dense, and nonvolatile memory technology on the CMOS platform. Another class of challenges is to extend information processing substantially beyond that attainable by CMOS using an innovative combination of, perhaps, new materials, devices and architectural means for representing, processing, transmitting, and storing information. These Difficult Challenges will be organized to separately discuss Device and Materials Difficult Challenges.

Device Technologies

Difficult Challenges related to emerging research devices are further divided to those related to memory technologies and those related to logic devices. One such challenge is the need of a new memory technology that combines the best features of current volatile and non-volatile memories in a fabrication technology compatible with CMOS process flows. This would provide a memory device fabrication technology required for both stand-alone and embedded memory applications. The ability of an microprocesser unit (MPU) to execute programs is limited by interaction between the processor and the memory, and scaling does not automatically solve this problem. The current evolutionary solution is to increase MPU cache memory, thereby increasing the floor space that static RAM (SRAM) occupies on an MPU chip. This trend eventually leads to a decrease of the net information throughput. In addition, volatility of semiconductor memory requires external storage media with slow access (e.g., magnetic hard drives, optical CD, etc.). Therefore, development of electrically accessible non-volatile memory with high speed and high density would initiate a revolution in computer architecture. This development would provide a significant increase in information throughput even if traditional benefits of scaling were fully realized for nanoscale CMOS devices.

A longer-term challenge for information processing or logic devices is invention and reduction to practice of a new manufacturable information processing technology addressing “beyond CMOS” applications. Solutions to this challenge could open new opportunities for nanoelectronics beyond the end of CMOS scaling by extending current and enabling new information processing functionalities.

Table 52 Difficult Challenges—Emerging Research Device Technologies

Difficult Challenges ≥32 nm

Summary of Issues

Development and implementation into manufacturing of a non-volatile memory technology, scalable beyond 32 nm, combining the best performance features of both volatile and non-volatile memory technologies for both stand-alone and embedded applications.

Identification of the most promising technical approach(es) to obtain electrically accessible, high-speed, high-density, low-power, non-volatile RAM

Development of a manufacturable, cost-effective fabrication technology integrable with the process flow for CMOS logic providing for seamless integration onto a CMOS platform

Difficult Challenges <32 nm




Toward the maturation of CMOS scaling or beyond, discovery, reduction to practice, and implementation into manufacturing of novel, non-CMOS devices and architectures integrable (monolithically, mechanically, or functionally) with a CMOS platform technology.

  • 1D to extend charge based devices.

  • Articulate the fundamental physical principles needed to develop new device technologies.

  • Find a new information processing technology that addresses these fundamental principles (see the section entitled “Fundamental Guiding Principles”).

  • Make emerging logic and memory devices compatible. (A new logic technology may require a new compatible memory technology.)

  • Integrate the materials, device and architectural communities to interact and collaborate in discovering a new information processing technology.




No current approaches support the information processing technology required for “Beyond CMOS” satisfying the need for additional decades of functional scaling.

Discovery and reduction to practice of new, low-cost methods of manufacturing novel information processing technologies.

Any new technology for information processing must be compatible with the new memory technology discussed above; i.e., the logic technology must also provide the access function in a new memory technology.

A knowledge gap exists between materials behaviors and device functions.

Current metrologies examine fixed material states, but do not probe the state change dynamics.

Materials Technologies

The most difficult challenge for Emerging Research Materials is to deliver materials with controlled properties that will enable operation of emerging research devices in high density at the nanometer scale. To improve control of material properties for high-density devices, collaboration and coordination of synthesis with new and improved metrology and modeling must be undertaken. Improved metrology and modeling are needed to guide synthesis in developing material composition and nanostructure to produce materials with controlled, reproducible properties critical to device operation.

Each of the difficult challenges related to materials is crucial to progress in the technologies, and will require significant collaboration between synthesis, characterization, and modeling to enable extraction of critical properties for analysis of the potential performance in different device structures. Improving and optimizing materials requires understanding of the relationship between synthesis conditions, the resulting composition and structure, and how this affects the functional performance of the material. Thus, characterization must be done to establish the relationship between composition, structure, and functional properties and establishing models will help accelerate the optimization of the materials properties. As devices based on these materials are explored, models of the properties may enable evaluation of new device concepts with simulation. As devices are fabricated, different properties may need to be optimized to make them function, so models relating structure and composition to functional properties may accelerate material improvement. As results from controlled well-characterized experiments results are extracted, it would be valuable to establish a knowledge base to accelerate the development of devices, phenomenological models and ab initio models for nanometer-scale structured materials. In some cases, required metrology capabilities are research tools and have limited availability, so coupling of critical experiments with the required metrology tools may be challenging.

Table 53 Difficult Challenges—Emerging Research Materials Technologies

Difficult Challenges >32 nm

Summary of Issues

1D Charge State

Nanotube and nanowire properties, bandgap energy and carrier type, and mobility vary greatly at growth and are controlled by variations in composition, diameter and nanometer scale structure.

Nanotubes and nanowires grow in random locations and orientations, which is incompatible with high density memory and logic applications.

Difficult Challenges <32 nm

Summary of Issues

Molecular State: Molecules with Controllable, Reproducible Switching Mechanisms

Molecular switching is often highly variable between device lots fabricated with the same chemicals and materials.

Contact formation and bond structure may require atomic level control.

While groups have been able to fabricate devices that exhibited charge storage, complex interactions have been observed with contact materials and redox reactions, but it is often difficult to determine whether switching and transport are through molecular transport or other mechanisms.

No metrology tools are available to measure atomic structure details in carbon-based molecules embedded between two contact layers.

Spin State: Materials that Enable Spin Gain at Room Temperature and Dissipationless Transport

Ferromagnetic (FM) semiconductors only work at low temperatures < 200 K; need a room temperature FM semiconductor.

New materials are needed that can enable spin amplification (gain).

Strongly Correlated Electron State

Materials with strongly correlated electron states have unique complex interactions between electric and magnetic properties, with complex ferromagnetic, anti-ferromagnetic phase transitions that may support spontaneous spin precipitation. The challenge is to determine whether these properties can be used to enable new devices at the nanometer scale.

Nanometer Scale Contact and Interface Formation

Materials and processes for establishing interfaces, such as contacts, passivation, etc., must produce interfaces that do not detrimentally affect the state variable or carrier of the state variable, and meet the functional requirements for the device, such as carrier transport.

At the nanometer scale, interface materials must have good adhesion, which requires bonding, without detrimentally changing the properties of the device material.

Assembly of Nano-structured Materials

Nanostructure materials such as carbon nanotubes (CNTs) or molecules must be assembled in defined locations with controlled orientation and reproducible properties. (CNTs grow in random locations with random orientations.)

Molecules only self-organize on a small number of material surfaces and require thiol functionalization for assembly on Au and defect formation is not understood.
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