Research Interests vlsi and Parallel Processing. Data Security and Fault Tolerance. Multimedia and Neural Networks. Education




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Curriculum Vitae Chang N. Zhang

curriculum vitae

Chang N. Zhang


Professor

Dept. of Computer Science

University of Regina

Regina, SK S4S 0A2

Canada

tel: 306-585-4598

e-mail: zhang@cs.uregina.ca

http://www.cs.uregina.ca/~zhang

Research Interests


VLSI and Parallel Processing. Data Security and Fault Tolerance. Multimedia and Neural Networks.


Education


Ph.D. in Computer Science, 1988, Southern Methodist University, Dallas, TX, USA

B.S. in Computational Math, 1965, Shanghai University, Shanghai, China


Professional Experience


2001 – present Professor, in Dept. of Computer Science, University of Regina.

1995 – 2000 Associate Professor in Dept. of Computer Science, University of Regina.

1997 – present Adjunct Professor in Telecommunication Research Labs (TRLabs).

1990 – 1995 Assistant Professor in Dept. of Computer Science, University of Regina.

1988 – 1990 Research Assistant Professor in Dept. of Computer Science, Concordia University.

Research Associate in VLSI group, Centre de Recherche Informatique de Montreal (CRIM).

1984 – 1987 Research Assistant in Dept. of Computer Science and Engineering, Southern Methodist University.

1983 – 1984 Visiting Scholar in Dept. of Computer Science and Engineering, Southern Methodist University.

1982 – 1983 Visiting Scholar in Dept. of Computer Science, The Pennsylvania State University.

1965 – 1982 Lecturer in Dept. of Computer Science, Shanghai University of Science & Technology.


Teaching Experience


CS250, CS400, CS402, CS802, CS840 and CS841 at University of Regina.


Research Funding (last 4 years)



2002-2005 NSERC Operating grant: 4 X 26,000

2002 NSERC Equipment grant: 22,695

2004 TRLabs grant: 4 X 24,000

2001 CMC Equipment Loan grant (with 5 others): 15,430

2000 CMC Equipment Loan Competition (with S. O’Leary and others, group of 5): 16,500

2000 NSERC Equipment grant: 17,688


current graduate students


Leon Pan, Ph.D. Yawen Wu, Ph.D.; C. Lai, Ph.D. Xiang Xiao M.Sc.


Professional Society Activities


Conference Co-chair, Session Chair, 2002 International Conference on Communications, Circuits and Systems, Chengdu, China, June 2002.

Program Committee, 2001 International Conference on Parallel and Distributed Computing Systems (PDCS 2001), Dallas Aug. 2001.

Program Committee, 2000 International Conference on Parallel and Distributed Processing, Las Vegas, July 2000.

Program Committee, 2000 International Conference on Image Science, Systems and Technologies, Las Vegas, July 2000.

Program Committee, 1999 International Conference on Parallel and Distributed Processing, Las Vegas, July 1999.

Program Committee, 1999 International Conference on Image Science, Systems and Technologies, Las Vegas, July 1999.

Session Chair, 1999 Wireless Conference, Calgary, July 1999.

Program Committee, Parallel Processing Conference 97. Bonn, Germany, Sept. 1997.

Session Chair, International Conference on Computer Simulation and Modeling ‘93, Beijing, Aug. 1993.

Session Chair, 4th International. Conf. on Parallel and Distributed Computing and System, Washington D. C., Oct. 1991.

Session Chair, International Conference on Computer & Applications, Beijing, Aug. 1984.

Reviewers for NSERC, NSF, Micronet, IEEE Trans. on Computers, VLSI, Neural networks, and other journal and conferences.


Refereed Publications


Journal Papers

  1. C. N. Zhang and C. Lai, A Systematic Approach for Encryption and Authentication with Fault Tolerance, Computer Networks, 45(2004), pp 143-154.




  1. Hua Li and C. N. Zhang, A Cellular Automata Based Reconfigurable Architecture for Hybrid Cryptosystems, The Computer Journal, Vol. 47, No. 3, 2004, pp 320-328.




  1. C. Yang and C. N. Zhang, “XML for RBAC Administration in Distributed Systems”, International Journal of Computers and Their Applications, Jun. 2004.




  1. C. N. Zhang and H. Li, Design of Reconfigurable VLSI Architecture for Hybrid Arithmetic in GF (2**M), The Computer Journal, Vol. 46, No. 4, 2003, pp 450-460.




  1. C. Yang and C. N. Zhang, “An XML-Based Administration Method on Role-Based Access Control in the Enterprise Environment”, accepted and to be published in Information Management and Computer Security, Vol. 11, No. 5, 2003.




  1. C. N. Zhang and C. Yang, “Integrating Object Oriented Role-based Access Control Model with Mandatory Access Control Principles”, accepted and to be published in the Journal of Computer Information Systems, spring 2003.




  1. C. N. Zhang and X. Wu, “A Hybrid Approach of Wavelet Packet and Directional for Image Compression”, International Journal of Image Systems & Technology, Vol. 12, pp 51-55, 2002.




  1. C. N. Zhang and C. Yang, “Towards a More Complete Model of Role-based Access Control in Distributed System”, Journal of Information Science and Engineering, Vol.18 No. 6, pp 871-889, Nov. 2002.




  1. C. N. Zhang and C. Yang, “Designing a Complete Model of Role-Based Access Control System for Distributed Networks”, Journal of Information Science and Engineering, Vol. 18, No. 6, pp 871-889, 2002.




  1. C. N. Zhang and C. Yang, “Information Flow Analysis on Role-Based Access Control”, Information Management and Computer Security, Vol. 10, No. 5, pp 225-236, 2002.




  1. C. N. Zhang and H. Li, “A 4-Bits Serial Modular Multiplier Applied to RSA”, Iranian Journal of Electrical and Computer Engineering, Vol. 1, No. 1, pp. 11-20, 2002.




  1. H. Li and C. N. Zhang, “A Fast Algorithm for Multiplication on Elliptic Curves”, Canadian Journal of Electrical and Computer Engineering, Vol. 27, No. 2, pp. 61 - 65, 2002.




  1. H. Li and C. N. Zhang, “Efficient Cellular Automata Based Versatile Multiplier for GF (2m)”, Journal of Information Science and Engineering, Vol. 18, No. 4, pp. 479-488, 2002.




  1. C. N. Zhang, H. Li, N. Zhang, and J. Xie, “A DSP based POD Implementation for High Speed Multimedia Communications”, EURASIP Journal on Applied Signal Processing, Vol. 2002, No. 9, pp 975-980, Sept. 2002.




  1. H. Li and C. N. Zhang, “Low-Complexity Versatile Finite Field Multiplier in Normal Basis”, EURASIP Journal on Applied Signal Processing, Vol. 2002, No.9, pp 954-960, Oct. 2002




  1. C. N. Zhang and C. Yang, “Integrating Object Oriented Role-based Access Control with Mandatory Access Control Principles”, accepted by The Journal of Computer Information System, Oct. 2002.




  1. C. N. Zhang and H. Li, “A Cellular Automata Based Reconfigurable Architecture for Hybrid Cryptosystems”, accepted by the Computer Journal, Oct. 2002.




  1. J. H. Weston, C. N. Zhang and H. Li, “Some Space Considerations on VLSI Systolic Array Mappings”, IEEE Trans. on Circuits and Systems II, Vol. 48, No. 4, pp 419-424.




  1. C. N. Zhang, M. Zhao and M. Wang, “Logic Operations Based on Single Neuron Rational Model”, IEEE Trans. on Neural Networks, Vol. 11, No. 3, pp 739-747, May 2000.




  1. C. N. Zhang, “An Integrated Approach for Fault Tolerance and Digital Signature in RSA”, IEE Proc.-Comp. Digit. Tech. Vol. 146, No. 3, pp 151-159, May 1999.




  1. C. N. Zhang, M. Zhao and M. Wang, “Single Neural Rational Model of Arithmetic and Logic Operations”, Connection Science, Vol. 11, No. 1, pp 73-90, 1999.




  1. C. N. Zhang, M. Bachtiar and W. K. Chou, “Optimal Fault-Tolerant Design Approach for VLSI Array Processors”, IEE Proc-Comp. Digit. Tech., Vol. 144, No. 1, pp 15-21, Jan. 1997.




  1. C. N. Zhang, M. Wang and W. K. Chou, “A Bidirectional Vector Associative Memory Architecture with Application to Neural Networks”, Microelectronics Journal, Vol. 27, No. 8, pp 713-722, Nov. 1996.




  1. M. Wang and C. N. Zhang, “Neural Rational Arithmetic Operations Revealed in Phase Space of Gated Conductances”, Biophysics Journal, Vol. 71, No. 5, pp 2380-2394, 1996.




  1. C. N. Zhang, A. G. Law, A. Rezazadeh and C. C. Tseng, “Designing VLSI Systolic Arrays with Complex Processing Elements”, Journal of High Performance Computing, Vol. 2, No. 1, pp 43-48, Nov. 1995.




  1. C. N. Zhang, M. Wang and C. C. Tseng, “Residue Systolic Implementations for Neural Networks”, Journal of Neural Computing and Applications, Vol. 3, pp 149-156, Dec. 1995.




  1. C. N. Zhang, J. H. Weston and Y. F. Yan, “Determining Objective Functions in Systolic Array Designs”, IEEE Trans. on VLSI Systems, Vol. 2, No. 3, pp 357-360, 1994.




  1. C. N. Zhang, H. F. Li and R. Jayakumar, “A Systematic Approach for Designing Concurrent Error Detecting Systolic Arrays Using Redundancy”, Journal of Parallel Computing, Vol. 19, pp 745-764, May 1993.




  1. C. N. Zhang, B. Shirazi and D. Y. Y. Yun, “An Efficient Algorithm and Parallel Implementation for Binary and Residue Number Systems”, Journal of Symbolic Computations, Vol. 15, pp 451-462, Apr. 1993.




  1. C. N. Zhang, “An Improved Binary Algorithm for RSA”, International Journal of Computer & Math with Applications, Vol. 25, No. 6, pp 15-24, Jan. 1993.




  1. H. F. Li, C. N. Zhang and R. Jyakumar, “Space-time Mapping, Latency of Data Flow and Concurrent Error Detection in Systolic Arrays”, IEE Proc.-Comp. Digit. Tech., Vol. 140, No. 1, pp 33-44, Jan. 1993.




  1. C. N. Zhang and B. S. Christian, “A Systematic Approach to Design of Fault Tolerant Systolic Arrays”, Congresses Numerantium, Vol. 92, pp 213-224, Apr. 1993.




  1. M. Wang and C. N. Zhang, “2-D Mapping of Chaotic Behavior in Simple Neural Networks”, Congresses Numerantium, Vol. 92, pp 155-160, Apr. 1993.




  1. A. G. Law, C. N. Zhang, A. Rezazadeh and L. Jodar, “Evaluation of a Rational Function”, Numerical Algorithms, Vol. 3, pp 265-272, Dec. 1992.




  1. C. N. Zhang, “Systematic Designing Systolic Arrays for Computing Multiple Problem Instances”, Microelectronics Journal, Vol. 23, No. 7, pp 543-553, Oct. 1992.




  1. A. Rezazadeh, C. N. Zhang, A. G. Law and J. H. Weston, “A Role for Generalized Inverses in Designing Systolic Arrays”, Congresses Numerantium, Vol. 87, pp 51-57, Mar. 1992.




  1. C. N. Zhang and H. D. Cheng, “High-Speed Single Error Correcting Converter for Residue Number Processing”, IEE Proc.-Comp. Digit. Tech., Vol. 138, No. 4, pp 177-182, Jul. 1991.




  1. B. Shirazi, D. Y. Yun and C. N. Zhang, “RBCD: Redundant Binary Coded Decimal Adder”, IEE Proc.-Comp. Digit. Tech., Vol. 136, No. 2, pp 156-160, Mar. 1989.


Conference Papers


  1. C. N. Zhang and H. Zhong, An integrated Approach for Database Security and Fault Tolerance, International Conference on Information Technology, Las Vegas, April 2004, pp 762 – 766.




  1. C. N. Zhang and Z. Li, An Efficient Group Key Management Scheme for Secure Multicast with Multimedia Application, The first Euro Public Key Infrastructure, Greek, June, 2004, pp 364-378.




  1. C. N. Zhang and Y. Wu, “A Fast Encryption Algorithm for MPEG-2 videos”, submitted to the 15th International Conference on Wireless Communications, pp183-188, Calgary, Alberta, Canada, July 7-9, 2003.




  1. C. N. Zhang and C. Li, “Design and Implementation of Secure DSP Implementation", accepted by 2003 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM’03), pp 557 – 560, 2003.




  1. C. Yang and C. N. Zhang, “An Approach to Secure Information Flow Analysis on Object-oriented Role-based Access Control Model”, 18th ACM Symposium on Applied Computing, special track on Computer Security, pp 302-306, Melbourne, Florida, USA, March 9-12, 2003.




  1. C. Yang and C. N. Zhang, “Secure Web-based Applications with XML and RBAC”, accepted by 4th Annual IEEE Information Assurance Workshop, United States Military Academy, West Point, New York, June 18-20, 2003.




  1. C. Yang and C. N. Zhang, “Designing Secure E-Commerce with Role-based Access Control”, accepted by IEEE Conference on E-Commerce (CEC03), Newport Beach, California, USA, June 24-27, 2003.




  1. C. Yang and C. N. Zhang, “An XML-based Administration Method on Role-based Access Control in the Enterprise Environment”, 5th International Conference on Enterprise Information Systems, pp 646-649, Anders, France, April 23-26, 2003.




  1. C. Yang and C. N. Zhang, “An Approach of XML-based Administration and Information Flow Analysis for Role-based Access Control Model”, accepted by 5th International Conference on Information Security and Cryptology (ICISC 2002), Nov. 2002, Seoul, Korea.




  1. C. N. Zhang and H. Li, “Reconfigurable Pipelined Cellular Automata Array for Cryptography”, 2002 International Conference on Communications, Circuits and Systems, Chengdu, China, June 2002, pp 1213-1217.




  1. Y. Wu and C. N. Zhang, “A Rough Neural Network for Material Proportion System”, 2002 International Conference on Communications, Circuits and Systems, Chengdu, China, June 2002, pp 1189-1193.




  1. C. N. Zhang and Y. Wu, “A Material Proportioning Controller Based on Rough Neural Network”, Proceedings of IASTED International Conference on Control and Applications, pp132-136, Cancun, Mexico, May 20-22, 2002.




  1. H. Li and C. N. Zhang, “A Low-Complexity Pipelined Architecture for Versatile Normal Basis Multiplier in GF (2n)”, The International Workshop on System on Chip for Real-time Applications, July 2002, Banff, pp 145-152.




  1. C. N. Zhang and C. Yang, “An Object-Oriented RBAC Model for Distributed Systems”, 2001 IEEE/IFIP Conference on Software Architecture (WICSA 2001), Amsterdam. Netherlands, August 2001, pp 24-32.




  1. C. N. Zhang, W. K. Chou, N. N. Zhang and J. Xie, “A DSP Based POD Implementation for High Speed Multimedia Communications”, accepted by 14th International Conference on Parallel and Distributed Computing Systems, Dallas, August 2001, pp 206-210.




  1. C. N. Zhang and H. Li, “A Fast VLSI Algorithm for Multiplication on Elliptic Curves”, 2001 IEEE Workshop on Information Assurance and Security, West Point, June 2001, pp 175-178.




  1. C. N. Zhang and C. Yang, “Specification and Enforcement of Object-Oriented RBAC Model”, 2001 IEEE Canadian Conference on Electrical and Computer Engineering, Toronto, May 2001.




  1. C. N. Zhang, J. Xie and S. Li, “Watermarking and Selective Encryption Algorithms for JEPG Images”, 13th International Conference on Computer Applications in Industry and Engineering, Hawaii, Nov. 2000, pp 132-134.




  1. M. Chen, C. N. Zhang and J. Li, “A Parallel Approach for Solving Multiple Machine Job Scheduling Problem”, 13th International Conference on Computer Applications in Industry and Engineering, Hawaii, Nov. 2000, pp 32-35.




  1. C. N. Zhang. C. Yang and A. Kostiuk, “A Secure MP3 Codec Supporting Encryption and Watermarking”, 13th International Conference on Parallel and Distributed Computing Systems, August 2000, Las Vegas, pp 640-645.




  1. C. N. Zhang and X. Wu, “Scheme Comparison of Video Compression with 3-D Wavelet Transform”, 13th International Conference on Parallel and Distributed Computing Systems, August 2000, Las Vegas, pp 610-614.




  1. C, N. Zhang and H. Li, “DCSA Systolic Array for Modular Multiplication and RSA Encryption”, 2000 International Conference on Parallel and Distributed Processing Techniques and Applications, June 2000, Las Vegas, USA, pp 1667-1673.




  1. H. Waston, C. N. Zhang and H. Li, “Some Space Considerations of VLSI Systolic Array Mappings”, the 7th International Conference on Parallel and Distributed Systems (ICPADS-2000), July 2000, Iwate, Japan, pp 375-381.




  1. C. N. Zhang, C. Lai and A. Kostiuk, “High-Speed Software Cellular Automata Cryptosystem for Multimedia Applications”, 12th International Conference on Wireless Communications (Wireless ‘2000), Calgary, July 2000, pp 583-591.




  1. C. N. Zhang, C. Yang and A. Kostiuk, “An Improved Selective Encryption Algorithm For MP3”, 12th International Conference on Wireless Communications (Wireless ‘2000), Calgary, July 2000, pp 592-599.




  1. C. N. Zhang and M. Zhao, “Multi-Mode Single Neural Arithmetics and Logics”, 1999 IEEE Pacific Rim Conference on Communication and Signal Processing, Victoria, BC, August 1999, pp 428-431.




  1. C. N. Zhang, M. Deng, and R. Mason, “A VLSI Programmable Cellular Automata Array for Multiplication in GF (2n)”, 1999 International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, July 1999, pp 1118-1123.




  1. R. Mason, T. Peng, and C. N. Zhang, “Implementation of a 1.6 Gbps Cellular Automata Encryption IC”, Wireless ‘99, Calgary, July 1999, pp 323-327.




  1. C. N. Zhang and X. Wu, “A Hybrid Approach of Wavelet Packet and Directional Decomposition for Image Compression”, IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton, May 1999, pp 755-760.




  1. C. N. Zhang and D. Chan, “Automatic Feedback Thesaurus for Web Search”, The Third Pacific-Asia Conference on Knowledge Discovery and Data Mining, Beijing, China, April 1999, pp 21-25.




  1. C. N. Zhang, D. Chan, and C. C. Lui, “Text Retrieval System Based on a Parallel Processing Scheme”. The Third Pacific-Asia Conference on Knowledge Discovery and Data Mining, Beijing, China, April 1999, pp 32-64.




  1. C. N. Zhang, M. Deng, and R. Mason, “Improved Algorithms and Hardware Implementations for Key Distribution Using Programmable Cellular Automata”, 14th Annual Computer Security Applications Conference, Arizona, Dec. 1998, pp 244-249.




  1. C. N. Zhang, “An Integrated Approach for Fault Tolerance and Digital Signature in RSA”, 14th International Information Security Conference, Vienna, August 1998, pp 85-95.




  1. C. N. Zhang and J. Xu, “Adaptive Hierarchical Block Truncation Coding”, 1998 International Conference on Imaging Science, Systems, and Technology, Las Vegas, July 1998, pp 73-77.




  1. C. N. Zhang, M. Wong and D. Chang, “Parallel Processing of a Information Retrieval System”, 1998 International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, July 1998, pp 1740-1745.




  1. R. Mason, C. N. Zhang, S. Lee and M. Deng, “High Speed Encryption Using a 2-D Cellular Automata Implemented in a Single FPGA”, Wireless ‘98, Calgary, July 1998, pp 325-331.




  1. R. Mason, T. Peng and C. N. Zhang, “264Mbit/s Encryption Using a 2-D Pipeline/Parallel FPGA Cellular Automata, FPD ‘98, Montreal, June 1998, pp 141-144.




  1. C. N. Zhang, Y. Xu and C. C. Wu, “A Two-Level Pipelined Bit-Serial VLSI Array for RSA”, 1997 IEEE Pacific Rim Conference on Communication and Signal Processing, Victoria, BC, August 1997, pp 523-526.




  1. D. Chan, C. N. Zhang, M. Wong and S. Z. Li, “A Parallel Text Retrieval System and its Application to Web Search”, 1997 International Workshop on Computational Science and Engineering, Hefei, China, May 1997, pp 231-236.




  1. M. Wang and C. N. Zhang, “Human Number Production: Symbolic Knowledge Representation in Neural Architectures”, 9th International Conference on Computer Applications in Industry and Engineering, Orlando, Florida, Dec. 1996, pp 154-157.




  1. C. N. Zhang and M. Wang, “A Generalized Square-Multiply Algorithm for RSA and Its VLSI Array Implementation”, 1996 International Conference on Parallel and Distributed Processing Techniques and Applications, Sunnyvale, CA, Aug. 1996, Vol. 1, pp 1-11.




  1. C. N. Zhang, A. Zhu and R. Mason, “A VLSI Programmable Cellular Automata Cipher for Secure Video on Demand Systems”, 8th International Conference on Wireless Communications, Calgary, July 1996, pp 261-267.




  1. B. S. Christian, C. N. Zhang and R. Mason, “A VLSI Router for High-Speed Networks”, IEEE Canadian Conference on Electrical and Computer Engineering, Calgary, May 1996, pp 154-157.




  1. T. M. Bachtiar, Y. Xu and C. N. Zhang, “A Secure Video on Demand System”, IEEE Pacific Rim Conference on Communications, computers, and Signal Processing, May 1995, Victoria, BC, pp 304-307.




  1. N. Shan, C. N. Zhang, H. J. Hamilton and N. Cercone, “Minimizing the Rules of a Fuzzy Logic System by Using Rough Sets”, Pacific-Asian Conference on Expert Systems, Huangshan, China, May 1995, pp 198-204.




  1. X. D. Yang, M. Wang, N, Shan and C. N. Zhang, “Automatic Generation of Segmentation Rules in Multi resolution Wavelet Transformed Images”, Pacific-Asian Conference on Expert Systems, Huangshan, China, May 1995, pp 535-537.




  1. C. N. Zhang, M. Bachtiar and W. K. Chou, “An Optimal Fault-Tolerant Design Approach for Array Processors”, 1994 International Conference on Parallel and Distributed Systems, Taiwan, Dec. 1994, pp 348-353.




  1. N. Shan and C. N. Zhang, “A Parallel Processing for Generating Maximally General Decision Rules Based on Rough Set Theory”, The Sixth International Conference on Artificial Intelligence and Expert Systems Applications, Dec. 1994, Houston, TX, pp 619-624.




  1. C. N. Zhang, W. Chan and M. Bachtiar, “Token Ring Arbitration Circuits for Dynamic Priority Algorithms”, 37th Midwest Symposium on Circuits and Systems, Aug. 1994, Lafayette, Louisiana, pp 74-77.




  1. M. Wang and C. N. Zhang, “A Canonical Form of Neural Dynamics in Somatic Reference Systems”, The 1994 IEEE International Conference on Neural Networks, June 1994, Orlando, Florida, pp 1012-1017.




  1. C. N. Zhang, M. Wang, C. C. Tseng and W. K. Chou, “Residue Array Processors for Neural Networks”, International Conference on Parallel and Distributed Systems, Dec. 1993, Taipei, Taiwan, pp 717-721.




  1. Z. Lin, C. C. Tseng and C. N. Zhang, “The Design of an Efficient Data-Driven Pipelined Computer Architecture”, International Conference on Parallel and Distributed Systems, Dec. 1993, Taipei, Taiwan, pp 158-161.




  1. H. D. Cheng, C. Xia and C. N. Zhang, “A Parallel Approach to Character Recognition and its VLSI Implementation”, SPIE Visual Communications Conf. ‘93, Nov. 1993, Cambridge, MA, pp 62-73.




  1. A. G. Law, A. Rezazadeh, J. Walters, J. H. Weston and C. N. Zhang, “A Simulation System for Systolic Arrays”, European Simulation Symp., Oct. 1993, Delft Netherlands, pp 495-500.




  1. M. Wang, C. N. Zhang and G. Z. Yao, “On the Canonical Form of Dynamics and a Dual System Model for Neural Networks”, International Joint Conf. on Neural Networks, Oct. 1993, Nagoya, Japan, pp 421-424.




  1. G. C. Hau and C. N. Zhang, “A Parallel Algorithm for Thinning Binary Patterns”, The First Chinese Word Congress on Intelligent Control and Intelligent Automation, Aug. 1993, Beijing, pp 1749-1754.




  1. C. N. Zhang, M. Wang and G. Z. Yao, “Calculus Relations in Spatial Summation and Determination of Macro Connection in Neural Networks”, International Conf. on Neural Networks, March 1993, San Francisco, pp 365-370.




  1. C. N. Zhang and G. C. Hsu, “A Two-level Pipelining Implementation for RSA Cryptosystem”, International Computer Symp., Dec. 1992, Taichung, Taiwan, pp 179-186.




  1. Y. F. Yan, C. N. Zhang, A. G. Law and J. H. Weston, “A Systolic Array Design Environment”, Canadian Conf. on VLSI, Halifax, Oct. 1992, pp 284-291.




  1. Y. F. Yan, C. N. Zhang and A. G. Law, “A Combined Static/Dynamic Data Compression Approach”, Canadian Conf. on Electrical and Computer Engineering, Toronto, Sep. 1992, MM10.11.1-MM10.11.4.




  1. C. N. Zhang, A. G. Law and A. Rezazadeh, “A Systematic Approach for Designing Systolic Arrays”, Second Great Lakes Symp. on VLSI, Kalamazoo, MI, Feb. 1992, pp 92-95.




  1. A. G. Law, C. N. Zhang, A. Rezazadeh and L. Jodar, “Evaluation of a Rational Function”, International Math. Congress on Extrapolation & Rational Approximation, Tenerife, Jan. 1992, pp 265-272.




  1. C. N. Zhang, H. F. Li and R. Jayakumar, “A General Model for Concurrent Error Detection in Systolic Arrays”, 4th International. Conf. on Parallel and Distributed Computing and Systems, Washington, D. C., Oct. 1991, pp 267-271.




  1. C. N. Zhang and H. D. Cheng, “Mapping Multiple Problem Instances into a Single Systolic Array with Application to Concurrent Error Detection”, IEEE 20th International Conf. on Parallel Processing, St. Charles, IL, Aug. 1991, pp I668-I669.




  1. H. D. Cheng and C. N. Zhang, “A Novel Neural Network for Program Solving”, International Conf. on Advanced Computer Tech., Reliable System, Bologna, Italy, May 1991, pp 497-501.




  1. C. N. Zhang and H. D. Cheng, “A High Speed Error Correcting Converter for Residue Number Processing”, International Conf. on Advanced Computer Tech., Reliable System, Bologna, Italy, May 1991, pp 816-820.




  1. C. N. Zhang, A. G. Law and A. Rezazadeh, “Designing VLSI Systolic Arrays with Complex Processing Elements”, First Great Lakes Symp. on VLSI, Kalamazoo, MI, Mar. 1991, pp 207-213.




  1. C. N. Zhang, “Concurrent Error Detection in Systolic Arrays”, 1990 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Grenoble, France, Oct. 1990, pp 91-95.




  1. C. N. Zhang, “Formal Verification of Systolic Networks Using Theorem Proving Techniques”, International Symp. on Computer Architecture and Signal Processing, Hong Kong, Oct. 1989, pp 116-119.




  1. H. F. Li, C. N. Zhang and R. Jayakumar, “Latency of Computational Data-flow and Concurrent Error Detection in Systolic Arrays”, Canadian Conf. on VLSI, Vancouver, BC, Dec. 1989, pp 251-258.




  1. C. N. Zhang and D. Y. Yun, “Parallel Algorithms and Systolic Designs for RSA Cryptosystems”, International Conf. on Systolic Arrays, San Francisco, CA, May 1988, pp 233-237.




  1. C. N. Zhang, B. Shirazi and D. Y. Yun, “VLSI Designs for Redundant Binary Coded Decimal Addition”, Phoenix Conf. on Computer and Communications (PCCC ‘88), Phoenix, AZ, Mar. 1988, pp 298-302.




  1. C. N. Zhang and D. Y. Yun, “Time-space Optimal Systolic Divider Using Redundant Binary Representation”, Second International Conf. on Computers and Applications, Beijing, China, June 1987, pp 423-427.




  1. C. N. Zhang and D. Y. Yun, “Parallel Designs for Chinese Remainder Conversion”, IEEE 16th International Conf. on Parallel Processing, St. Charles, IL, Aug. 1987, pp 557-559.




  1. C. N. Zhang, D. Y. Yun and B. Shirazi, “An Efficient Algorithm and VLSI Designs for Residue Conversion”, IEEE/ACM Fall Joint Conf., Dallas, TX, Oct. 1987, pp 390-396.


Chapters in Books:

  1. C. N. Zhang and M. Wang, “Multimode Single Neuron Arithmetics”, in Neural Network Systems Techniques and Applications published by Academic Press (editor: C. T. Leondes) 1998.




  1. C. N. Zhang, “Mapping Algorithms onto Concurrent Error Detecting Array Processors”, published by Science and Technology Publishing Corporation (editor: L. Tao) 1995.




  1. D. Y. Yun and C. N. Zhang, “Parallel Algorithms and Designs for Fundamental Operations in Cryptography”, in Progress in Computer Aided VLSI Design, Vol. 3, published by Ablex Publishing Corporation, Norwood, (editor: G. Zobrist) 1990.

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