Opening Ceremony and Committees Address by General Chair and Program Chair




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FULL PROGRAM


Monday 3rd October 2011


08:45 – 09:15

Opening Ceremony and Committees Address by General Chair and Program Chair


09:15 – 10:15

Keynote speech 1: Rigorous System Design (Grand Ballroom I)

Joseph Sifakis

CNRS-Grenoble INP-UJF, Verimag Laboratory, Grenoble, France


10:35 – 12:15

Session 1. Biomedical Sensors (Grand Ballroom II)


Organizer: Jun Ohta, Nara Institute of Science and Technology, Japan

Chair: Jun Ohta, Nara Institute of Science and Technology, Japan

Co-chair: Amine Bermak, The Hong Kong University of Science and Technology, Hong Kong SAR, China


1.1 A Low Cost CMOS Polarimetric Ophthalmoscope Scheme for Cerebral Malaria Diagnostics

Xiaojin Zhao1,2, Amine Bermak1, and Farid Boussaid3

1 The Hong Kong University of Science and Technology, Hong Kong SAR, China

2 Shenzhen University, China

3 The University of Western Australia


1.2 Multimodal Proton and Fluorescence Image Sensor for Bio Applications

Hirokazu Nakazawa, Makoto Ishida, and Kazuaki Sawada

Toyohashi University of Technology, Aichi, Japan


1.3 Fabrication of a Flexible Neural Interface Device with CMOS-based Smart Electrodes

Toshihiko Noda1, Takuya Kitao1, Takasuke Ito1, Kiyotaka Sasagawa1, Takashi Tokuda1, Yasuo Terasawa2, Hiroyuki Tashiro3, Hiroyuki Kanda4, Takashi Fujikado4, and Jun Ohta1

1 Graduate School of Materials Science, Nara Institute of Science and Technology, Japan

2 Vision Institute, NIDEK Co Ltd., Gamagori, Japan

3 Faculty of Medical Science, Kyushu University, Japan

4 Graduate School of Medicine, Osaka University, Japan


1.4 Micro CMOS Image Sensor for Multi-area Imaging

Kiyotaka Sasagawa, Hiroyuki Masuda, Ayato Tagawa, Takuma Kobayashi, Toshihiko Noda, Takashi Tokuda and Jun Ohta

Nara Institute of Science and Technology, Japan


---------------


Session 2. Digital design and architectures (Grand Ballroom III)


Chair: Shoushun Chen, Nanyang Technological University, Singapore

Co-chair: Ricardo Reis, UFRGS, Brazil


2.1 A Novel Low-Leakage 8T Differential SRAM Cell

Khawar Sarfraz

Lahore University of Management Sciences, Pakistan


2.2 Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors

Tso-Bing Juang1, Hsin-Hao Peng1, Chao-Tsung Kuo2

1 National Pingtung Institute of Commerce, Taiwan

2 National Quemoy University, Taiwan


2.3 STT-RAM based Energy-Efficiency Hybrid Cache for CMPs

Jianhua Li1, Chun Jason Xue1, Yinlong Xu2

1 City University of Hong-Kong, Hong Kong SAR, China

2 USTC, China


2.4 Embedded MRAM for High-speed Computing

Weisheng Zhao1, Lionel Torres2, Luis V. Cargnini2, Raphael M. Brum2, Yoann Guillemenet2, Gilles Sassatelli2, Yue Zhang1, Yahya Lakys1, Jacques O. Klein1, Dafiné Ravelosona1, Claude Chappert1

1 IEF University Paris-Sud/CNRS

2 LIRMM, University of Montpellier/CNRS


13:30 – 14:45

Session 3. Analog IC Design I (Grand Ballroom II)


Chair: Jose Manuel de la Rosa, IMSE-CNM-Universidad de Sevilla, Spain

Co-Chair: Jacob Wikner, Linköping University, Sweden


3.1 A High Efficiency Synchronous Buck Converter with Adaptive Dead Time Control for Dynamic Voltage Scaling Application

Shaowei Zhen, Bo Zhang, Ping Luo, Kang Yang, Xiaohui Zhu, Jiangkun Li

University of Electronic Science and Technology of China, Chengdu, China


3.2 Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test

Shakeel Ahmad, Jerzy Dabrowski

Linkoping University, Sweden


3.3 A Low-Power Ultra-Fast Capacitor-Less LDO With Advanced Dynamic Push-Pull Techniques

Xin Ming, Ze-Kun Zhou, Bo Zhang

University of Electronic Science and Technology of China, China


---------------


Session 4. Digital signal and image processing (Grand Ballroom III)


Chair: Jason Xue, City University, Hong Kong SAR

Co-chair: Luc Claesen, Hasselt University, Belgium


4.1 Generating High Tail Accuracy Gaussian Random Numbers in Hardware Using Central Limit Theorem

Jamshaid Sarwar Malik1, Jameel Nawaz Malik2, Ahmed Hemani1, N. D. Gohar2

1 KTH, Sweden

2 NUST SEECS Pakistan


4.2 Adaptive Priority Toggle Asynchronous Tree Arbiter for AER-based Image Sensor

Myat Thu Linn Aung, Anh Tuan Do, Shoushun Chen, Yeo Kiat Seng

Nanyang Technological University, Singapore


4.3 MUX-MCM Based Quantization VLSI Architecture for H.264/AVC High Profile Encoder

Yibo Fan1, Xiaoyang Zeng1, Ying Jiang2, Xinhua Chen2

1 Fudan University, China

2 Shandong University of Science and Technology, China


14:45 – 16:00

Poster Session 1 (Grand Ballrooms II and III)


Chair: Ngai Wong, The University of Hong Kong, Hong Kong SAR, China


P1.1 Topology Synthesis of Analog Circuits with Yield Optimization and Evaluation using Pareto Fronts

Oliver Mitea, Markus Meissner, Lars Hedrich

University of Frankfurt, Germany


P1.2 New 12-bit Source-Follower Track-and-Hold Circuit Suitable for High-Speed Applications

Marcel V. Campos1, Andre L. Fortunato2, Carlos A. R. Filho3

1 University State of Montes Claros, Brazil

2 University State of Campinas, Brazil

3 Federal University of ABC, Brazil


P1.3 A Low Loss Rectifier Unit for Biomedical Applications

Qingyun Ma, Mohammad Haider, Yehia Massoud

The University of Alabama at Birmingham, United States


P1.4 Prospects of 3D Inductors on Through Silicon Vias Processes for 3D ICs

Yiorgos Bontzios, Michael Dimopoulos, Alkis Hatzopoulos

Aristotle University of Thessaloniki, Greece


P1.5 Performance Evaluation of Air-gap-Based Coaxial RF TSV for 3D

Le Yu, Haigang Yang, Jia Zhang, Wei Wang

Institute of Electronics, Chinese Academy of Sciences, China


P1.6 Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC

Kai Lam, Terrence Mak, Chi-Sang Poon

1 Chinese University of Hong Kong, Hong Kong SAR, China

2 Newcastle University, United Kingdom

3 MIT, United States


P1.7 Worst Case Analysis for Evaluating VLSI Circuit Performance Bounds using optimization Method

Siwat Saibua, Liuxi Qian, Dian Zhou

University of Texas at Dallas, USA


P1.8 An Easily Testable Routing Architecture of FPGA

Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi

Kumamoto University, Japan


P1.9 Minimizing redundancy-based Motion Estimation design for High-Definition

Jeong Hoon Kim, In Jung Lyu, Hyun June Lyu, Jun Rim Choi

Kyungpook National University, South Korea


P1.10 FPGA Implementation of High Sampling Rate In-Car Non-Stationary Noise Cancellation Based on Adaptive Wiener Filter

Hong-Yuan Jheng1, Yen-Hsiang Chen1, Shanq-Jang Ruan1, Ziming Qi2

1 National Taiwan University of Science and Technology, Taiwan

2 Auckland Institute of Smart Technology, New Zealand


P1.11 MCM-Based Implementation of Block FIR Filters for High-Speed and Low-Power Applications

Pramod Kumar Meher, Yu Pan

Institute for Infocomm Research, Singapore


P1.12 1024-Point Pipeline FFT Processor with Pointer FIFOs based on FPGA

Guanwen Zhong, Hongbin Zheng, Zhenhua Jin, Dihu Chen, Zhiyong Pang

Sun Yat-sen University, China


16:00 – 17:15

Session 5. Low-power design (Grand Ballroom II)


Chair: José Ayala, Complutense University of Madrid, Spain

Co-chair: Luis Miguel Silveira, INESC ID, Portugal


5.1 A 230mV 8-bit Sub-threshold Microprocessor for Wireless Sensor Network

Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao

Shanghai Jiao Tong University, China


5.2 Exploiting Maximum Throughput in 3D Multicore Architectures with Stacked NUCA Cache

Asim Khan, Kyungsu Kang, Chong-Min Kyung

Korea Advanced Institute of Science and Technology, South Korea


5.3 Run-time Self-tuning Banked Loop Buffer Architecture for Power Optimization of Dynamic Workload Applications

Antonio Artes1, Jose L. Ayala1, Ashoka Visweswara Sathanur2, Jos Huisken3, Francky Catthoor4

1 Complutense University of Madrid, Spain

2 Holst Centre/IMEC, India

3 Holst Centre/IMEC, Netherlands

4 IMEC, Belgium


---------------


Session 6. Logic and high-level synthesis (Grand Ballroom III)


Chair: Dominique Borrione, TIMA Laboratory, France

Co-chair: Lionel Torres, University of Montpellier/LIRMM, France


6.1 Improvements to Satisfiability-Based Boolean Function Bi-Decomposition

Huan Chen, Joao Marques-Silva

University College Dublin, Ireland


6.2 A Hybrid Algorithm for the Optimization of Area and Delay in Linear DSP Transforms

Levent Aksoy1, Eduardo Da Costa2, Paulo Flores1, Jose Monteiro1

1 INESC-ID/IST, TU Lisbon, Portugal

2 Catholic University of Pelotas, Brazil


6.3 Early Planning for RT-Level Delay Insertion during Clock Skew-Aware Register Binding

Keisuke Inoue, Mineo Kaneko

JAIST, Japan


---------------

Tuesday 4th October 2011


08:45 – 09:45

Keynote speech 2: Design and Optimization of Thousand-core Systems: Challenges and Opportunities (Grand Ballroom I)

Radu Marculescu

Carnegie Mellon University, USA


09:45 – 10:45

Poster Session 2 (Grand Ballrooms II and III)

Chair: Jiang Xu, Hong Kong University of Science and Technology, Hong Kong SAR, China


P2.1 Frequency-Domain Transient Analysis of Multitime Partial Differential Equation Systems

Haotian Liu1, Fengrui Shi2, Yuanzhe Wang1, Ngai Wong1

1 The University of Hong Kong, Hong Kong SAR, China

2 Zhejiang University, Hang Zhou, China


P2.2 Post-Silicon Failing-Test Generation through Evolutionary Computation

Ernesto Sanchez, Giovanni Squillero, Alberto Tonda

Politecnico di Torino, Italy


P2.3 Communication-aware Middleware-based Design-Space Exploration for Networked Embedded Systems

Franco Fummi, Davide Quaglia, Francesco Stefanni

University of Verona, Italy


P2.4 A General Statistical Estimation for Application Mapping in Network-on-Chip

Naifeng Jing, Weifeng He, Zhigang Mao

Shanghai Jiao Tong University, China


P2.5 On-chip Structure and Addressing Scheme for 2-D Block Data Processing in a 64-core Array System

Jing Xie, Huimin Xing, Zhigang Mao

Shanghai Jiaotong University, China


P2.6 Communication Centric On-Chip Power Grid Models for Networks-On-Chip

Nizar Dahir, Terrence Mak, Alex Yakovlev

Newcastle University, United Kingdom


P2.7 A Clock-less Transceiver for Global Interconnect

Jianfei Jiang, Xu Wang, Weiguang Sheng, Weifeng He, Zhigang Mao

Shanghai Jiao Tong University, China


P2.8 An Optimized TTA-like Vertex Shader Datapath for Embedded 3D Graphics Processing Unit

Jizeng Wei, Yisong Chang, Wei Guo, Jizhou Sun

Tianjin University, China


P2.9 A Fault-tolerant NoC Design using Dynamic Reconfiguration of Partial-Faulty Routing Resources

Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui

The Hong Kong University of Science and Technology, Hong Kong SAR, China


P2.10 Communication Service for hardware tasks executed on dynamic and partial reconfigurable resource

Surya Narayanan1, Ludovic Devaux2, Daniel Chillet2, Sebastien Pillement2, Ioannis Sourdis3

1 Delf University of Technology, Netherlands

2 University of Rennes 1, Inria/Irisa, France

3 Chalmers University of Technology, Sweden


P2.11 Combinational Logic Synthesis for Material Implication

Anupam Chattopadhyay, Zoltan Rakosi

RWTH Aachen University, Germany


P2.12 SNM-Aware Power Reduction and Reliability Improvement in 45nm SRAMs

Seokjoong Kim, Matthew Guthaus

University of California Santa Cruz, USA


10:45 – 12:25

Session 7. MEMS and new devices (Grand Ballroom II)


Chair: Man Wong, Hong Kong University of Science and Technology, Hong Kong SAR, China

Co-Chair: Mohamad Sawan, Ecole Polytehcnique de Montreal, Canada


7.1 Self-dependent Equivalent Circuit Modeling of Electrostatic Comb Transducers for Integrated MEMS

Toshiyuki Tsuchiya, Hiroyuki Tokusaki, Yoshikazu Hirai, Koji Sugano, Osamu Tabata

Kyoto University, Japan


7.2 Wide-Band Piezoresistive Aero-Acoustic Microphone

Zhijian Zhou1, Libor Rufer2, Man Wong1

1 The Hong Kong University of Science and Technology, Hong Kong SAR, China

2 TIMA Laboratory, University of Grenoble/CNRS, France


7.3 Designs for Improving the Performance of an Electro-Thermal In-Plane Actuator

Man Ho Kwan1, Sichao Song1, Xing Lu1, Lei Lu1, Ying Khai Teh1, Ying Fei Teh1, Wing Cheung Chong1, Yan Gao1, William Hau1, Fan Xeng1, Man Wong1, Chunmei Huang2, Akira Taniyama2, Yoshihide Makino2, So Nishino2, Toshiyuki Tsuchiya2, Osamu Tabata2

1 The Hong Kong University of Science and Technology, Hong Kong SAR, China

2 Kyoto University, Japan


7.4 Uniform Carbon Nanotube Diameter and Nanoarray Pitch for VLSI of 16nm P-channel MOSFETs

Yanan Sun, Volkan Kursun

The Hong-Kong University of Science and Technology, Hong Kong SAR, China


---------------


Session 8. Emerging Technologies for Networks on Chip (Grand Ballroom III)


Organizer: Ian O'Connor, Lyon Institute of Nanotechnology, France

Chair: Ian O'Connor, Lyon Institute of Nanotechnology, France

Co-chair: Yuichi Nakamura, NEC, Japan


8.1 3D NoC Using Through Silicon Via: an Asynchronous Implementation
Pascal Vivet, Denis Dutoit, Yvain Thonnart and Fabien Clermidy

CEA-LETI, France


8.2 Thru-Chip Interface (TCI) for 3D Networks on Chip

Tadahiro Kuroda

Keio University, Japan

8.3 Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC)
Sébastien Le Beux1, Jelena Trajkovic2, Ian O’Connor1 and Gabriela Nicolescu2
1 Lyon Institute of Nanotechnology, France

2 Ecole Polytechnique de Montreal, Canada


8.4 Towards Future VLSI Interconnects Using Aligned Carbon Nanotubes

Yang Chai1, Minghui Sun1, Zhiyong Xiao1, Yuan Li1, Min Zhang1, and Philip C. H. Chan1,2

1 The Hong Kong University of Science and Technology, Hong Kong SAR, China

2 Hong Kong Polytechnic University, Hong Kong SAR, China


---------------


13:35 – 15:40

Session 9. Design for variability, fault tolerance, test (Grand Ballroom II)


Chair: Xiaoqing Wen, Kyushu Institute of Technology, Japan

Co-chair: Matthew Guthaus, University of California Santa Cruz, USA


9.1 New SEC-DED-DAEC Codes for Multiple Bit Upsets Mitigation in Memory

Li Yi Xiao1, Ming Zhu1, Hong Wei Luo2

1 Harbin Institute of Technology, China

2 National Key Laboratory of Science and Technology, China


9.2 Self-Test Method and Recovery Mechanism for High Frequency TSV Array

Jia Zhang, Le Yu, Haigang Yang, Yuanlu Xie, Fabiao Zhou, Wei Wang

Institute of Electronics, Chinese Academy of Sciences, China


9.3 Fault Tolerant Design for Low Power Hierarchical Search Motion Estimation Algorithms

Charvi Dhoot1, Vincent J. Mooney2, Shubhajit Roy Chowdhury3, Lap Pui Chau

1 International Institute of Information Technology, Hyderabad, India

2 Georgia Institute of Technology, USA

3 Nanyang Technological University, Singapore


9.4 Crosstalk Avoidance in NoC Channels Using Numeral-Based Data Coding

Mansour Shafaei, Ahmad Patooghy, Seyed Ghassem Miremadi, Somayyeh Taheri

Sharif University of Technology, Iran


9.5 On the Functional Test of Branch Prediction Units based on Branch History Table

Ernesto Sanchez, Matteo Sonza Reorda, Alberto Tonda

Politecnico di Torino, Italy


---------------


Session 10. Networks-on-Chip (Grand Ballroom III)


Chair: Wei Zhang, NanYang Technological University, Singapore

Co-Chair: Terrence Mak, Newcastle University, United Kingdom


10.1 Agent-based On-Chip Network Using Efficient Selection Method

Masoud Daneshtalab, Masoumeh Ebrahimi, Hannu Tenhunen

University of Turku, Finland


10.2 Network-on-Chip Multicasting with Low Latency Path Setup

Wenmin Hu1, Zhonghai Lu2, Axel Jantsch2, Hengzhu Liu1, Botao Zhang1, Dongpei Liu1

1 National University of Defense Technology, China

2 Royal Institute of Technology, Sweden


10.3 A Fault-Tolerant NOC using Combined Link Sharing and Partial Fault Link Utilization Scheme

Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui

The Hong Kong University of Science and Technology, Hong Kong SAR, China


10.4 Two-levels of adaptive buffer for virtual channel router in NoCs

Caroline Concatto1, Anelise Kologeski1, Luigi Carro1, Fernanda Kastensmidt1, Gianluca Palermo2, Cristina Silvano2

1 UFRGS, Brazil

2 Politecnico de Milano, Italy


10.5 System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic

Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi

University of Ferrara, Italy


---------------

16:00 – 17:15

Panel – SoC for biomedical applications : trends and challenges (Grand Ballroom III)

Organizers: Chi-Ying Tsui1, Salvador Mir2

1Hong Kong University of Science and Technology, Hong Kong SAR, China

2TIMA Laboratory, Grenoble, France


Panelists:


Mohamad Sawan, Ecole Polytehcnique de Montreal, Canada

Jun Ohta, Nara Institute of Science and Technology, Japan

Zhihua Wang, Tsinghua University, China

Yong Lian, National University of Singapore, Singapore


---------------

Wednesday 5th October 2011


08:45 – 09:45

Keynote speech 3: The Evolution of Fabless IC Industry in China: Past, Present, and Future

(Grand Ballroom I)

Ping K. Ko1, 2 and C. Patrick Yue2, 3

1 Silicon Federation Inc., Shanghai, China

2 The Hong Kong University of Science and Technology, Hong Kong SAR, China

3 University of California, Santa Barbara, CA, USA


09:45 – 10:30

PhD Forum (Grand Ballroom III)


Chair: Philip Mok, The Hong Kong University of Science and Technology, Hong Kong SAR, China


PhD.1 Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration

Norbert Abel

KIP Heidelberg, Germany


PhD.2 Hardware and Software Support for Parallel Programming Models on NoC-based MPSoCs

Gustavo Girão and Flávio Rech Wagner

UFRGS, Brazil


PhD.3 Hierarchical Interconnection for Low Power Circuits in Future Technologies

Debora Matos

UFRGS, Brazil


PhD.4 An Adaptive Multi-stage Rectifier for RF Energy Harvesting Applications

Xing Li, Chi-Ying Tsui and Wing-Hung Ki

The Hong Kong University of Science and Technology, Hong Kong SAR, China


PhD.5 Implementation of Decision Trees in a Configurable Multiprocessor Architecture

Bashar Badr, David Mulvaney and Vassilios Chouliaras

Loughborough University, United Kingdom


PhD.6 A Novel Modeling Methodology and Optimization Technique for RF Circuits using Design Of Experiments

Jai Narayan Tripathi

IIT Bombay, India


PhD.7 Adaptive Routing Scheme for Networks-on-Chip Using Minimal and Non-minimal Paths

Masoumeh Ebrahimi and Masoud Daneshtalab

University of Turku, Finland


10:30 – 12:10

Session 11. Analog IC Design II (Grand Ballroom II)


Chair: Jerzy Dabrowski, Linkopings University, Sweden

Co-chair: George-Jie Yuan, Hong Kong Univ. of Science and Tech., Hong Kong


11.1 Multirate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulator for Wideband Telecom

J. Gerardo García-Sánchez, Jose M. De La Rosa

CSIC/Universidad de Sevilla, Spain


11.2 A Voltage Mode Power Converter with the Function of Digitally Duty Cycle Tuning

Xiaohui Zhu, Ping Luo, Shaowei Zhen, Kang Yang, Jiangkun Li, Zekun Zhou

University of Electronic Science and Technology of China


11.3 A high performance band-pass DAC architecture and design targeting a low voltage silicon process

Brendan Mullane, Vincent O'Brien

University of Limerick, Ireland


11.4 Clockless asynchronous delta modulator based ADC for smart dust applications

Venkata Narasimha Manyam, Dhurv Chhetri, Jacob Wikner

Linköping University, Sweden


---------------


Session 12. Frontier in 3D Integration Engineering (Grand Ballroom III)


Organizers Terrence Mak1, Chi-Sang Poon2

1 Newcastle University, United Kingdom

2 MIT, USA

Chair: Terrence Mak, Newcastle University, United Kingdom

Co-chair: Chi-Sang Poon, MIT, USA

12.1 Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs


Xiaohang Wang1, Maurizio Palesi2, Mei Yang3, Yingtao Jiang3, Michael Huang4 and Peng Liu1

1 Zhejiang University, China

2 Kore University, Italy

3 University of Nevada Las Vegas

4 Rochester University

12.2 3-D Integration and the Limits of Silicon Computation


Dinesh Pamunuwa1, Matthew Grange1, Roshan Weerasekera1 and Axel Jantsch2

1 Lancaster University, United Kingdom

2 Royal Institute of Technology, Sweden

12.3 Architecture and Design of a Programmable 3D-Integrated Cellular Processor Array for Image Processing


Alexey Lopich, Piotr Dudek

University of Manchester, United Kingdom

12.4 Cycle Avoidance in 2D/3D Bidirectional Graphs Using Shortest-path Dynamic Programming Network


Kai-Pui Lam1, Terrence Mak2, and Chi-Sang Poon3

1 The Chinese University of Hong Kong

2 Newcastle University, UK

3 Massachusetts Institute of Technology


13:20 – 15:00

Session 13. Emerging Energy Harvesting Integrated Circuits and Systems (Grand Ballroom II)


Organizer: Dongsheng Ma, The University of Texas at Dallas, USA

Chair: Dongsheng Ma, The University of Texas at Dallas, USA

Co-chair: Alex Leung, CUHK, Hong-Kong SAR, China

13.1 A Battery-free Energy Harvesting System with the Switch Capacitor Sampler (SCS) Technique for High Power Factor in Smart Meter Applications


Tzu-Chi Huang1, Yao-Yi Yang1, Yu-Huei Lee1, Ming-Jhe Du2, Shih-Hsien Cheng2, and Ke-Horng Chen1

1 National Chiao Tung University, Hsinchu, Taiwan

2 Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan

13.2 A Subthreshold Digital Maximum Power Point Tracker for Micropower Piezoelectric Energy Harvesting Applications


Joey Sankman and Dongsheng Ma

The University of Texas at Dallas, USA

13.3 Interface Model Based Cyber-physical Energy System Design for Smart Grid


Janet Roveda, Susan Lysecky, Young-Jun Son, Hyungtaek Chang, Anita Annamalai and Xiao Qin

The University of Arizona, Tucson, USA

13.4 Design and Analysis of On-Chip Charge Pumps for Micro-Power Energy Harvesting Applications


Wing-Hung Ki1, Yan Lu1, Feng Su2 and Chi-Ying Tsui1

1 The Hong Kong University of Science & Technology, Hong Kong SAR, China

2 Broadcom Corporation, San Jose, CA, USA


---------------


Session 14. Modeling techniques for effective validation (Grand Ballroom III)


Chair: Masahiro Fujita, University of Tokyo, Japan

Co-chair: Matteo Sonza Reorda, Politecnico di Torino, Italy


14.1 SystemC-AMS behavioral modeling of a CMOS video sensor

Fabio Cenni1,2, Serge Scotti1, Emmanuel Simeu2

1 STMicroelectronics, Grenoble, France

2 TIMA Laboratory, University of Grenoble/CNRS, France


14.2 Context-aware compiled simulation of out-of-order processor behavior based on atomic traces

Roman Plyaskin, Andreas Herkersdorf

Technische Universitaet Muenchen, Germany


14.3 C-Routing: An Adaptive Hierarchical NoC Routing Methodology

Manas Kumar Puthal1, Virendra Singh2, Manoj Gaur1, Vijay Laxmi1

1 Malaviya National Institute of Technology, Jaipur, India

2 Indian Institute of Science, India


14.4 Positive Realization of Reduced RLCM Nets

Jorge Fernandez Villena, Luis Miguel Silveira

INESC ID / IST - TU Lisbon, Portugal


15:20 – 17:00

Session 15. Simulation and optimization (Grand Ballroom II)


Chair: Andreas BurgEPFL, Switzerland

Co-chair: Virendra Singh, Indian Institute of Science, Bangalore, India


15.1 3D-IC Floorplanning: Applying Meta-Optimization to Improve Performance

Felipe Frantz, Lioua Labrak, Ian O'Connor

Lyon Institute of Nanotechnology, France


15.2 Characterizing Statistical Cells Timing Metrics with Semi-Monte-Carlo Method

Zeqin Wu1, Philippe Maurine1, Nadine Azemard1, Gilles Ducharme2

1 LIRMM, University of Montpellier/CNRS

2 I3M / University of Montpellier/CNRS


15.3 A More Efficient Arrangement of the Sparse LU Factorization for the Large-Scale Circuit Analysis

Josef Dobes, David Cerny, Abhimanyu Yadav

Czech Technical University in Prague, Czech Republic


15.4 State Space Optimization within the DEVS Model of Computation for Timing Efficiency

H. Gregor Molter1, André Seffrin2, Sorin A. Huss1

1 Technische Universität Darmstadt, Germany

2 CASED, Germany


---------------


Session 16. Digital design and signal processing (Grand Ballroom III)


Chair: Luigi Carro, Universidad Federal Rio Grande do Sul, Brazil

Co-chair: Pramod Kumar Meher, Institute for Infocomm Research, Singapore


16.1 High-Throughput Pipelined Realization of Adaptive FIR Filter Based on Distributed Arithmetic

Pramod Kumar Meher, Sang Yoon Park

Institute for Infocomm Research, Singapore


16.2 A Full-mode FME VLSI Architecture Based on 8x8/4x4 Adaptive Hadamard Transform For QFHD H.264/AVC Encoder

Jialiang Liu1, Yibo Fan2, Xinhua Chen1, Xiaoyang Zeng2

1 Shandong University of Science and Technology, China

2 Fudan University, China


16.3 Robust Design of Sub-threshold Flip-Flop Cells for Wireless Sensor Network

Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao

Shanghai Jiao Tong University, China


---------------

17:00 – 17:15


Closing Session: Closing remarks by the conference chairs, Best paper award ceremony

(Grand Ballroom III)

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